Yifei Jiang 281d851303 target/riscv: raise exception to HS-mode at get_physical_address ... VS-stage translation at get_physical_address needs to translate pte address by G-stage translation. But the G-stage translation error can not be distinguished from VS-stage translation error in riscv_cpu_tlb_fill. On migration, destination needs to rebuild pte, and this G-stage translation error must be handled by HS-mode. So introduce TRANSLATE_STAGE2_FAIL so that riscv_cpu_tlb_fill could distinguish and raise it to HS-mode. Backports 33a9a57d2c31ec9ed68858911dc490b5de15f342		2021-03-08 14:43:00 -05:00
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insn_trans	target/riscv: Support the Virtual Instruction fault	2021-03-08 13:55:02 -05:00
cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 19:35:46 -04:00
cpu.c	qemu/atomic.h: rename atomic_ to qatomic_	2021-03-08 14:34:35 -05:00
cpu.h	target/riscv: raise exception to HS-mode at get_physical_address	2021-03-08 14:43:00 -05:00
cpu_bits.h	target/riscv: Support the Virtual Instruction fault	2021-03-08 13:55:02 -05:00
cpu_helper.c	target/riscv: raise exception to HS-mode at get_physical_address	2021-03-08 14:43:00 -05:00
cpu_user.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
csr.c	qemu/atomic.h: rename atomic_ to qatomic_	2021-03-08 14:34:35 -05:00
fpu_helper.c	target/riscv: Check nanboxed inputs to fp helpers	2021-03-08 12:31:18 -05:00
helper.h	target/riscv: Support the Virtual Instruction fault	2021-03-08 13:55:02 -05:00
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-28 19:00:23 -04:00
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn32-64.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2021-03-08 13:13:32 -05:00
insn32.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2021-03-08 13:13:32 -05:00
instmap.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
internals.h	target/riscv: Check nanboxed inputs to fp helpers	2021-03-08 12:31:18 -05:00
Makefile.objs	target/riscv: add vector configure instruction	2021-02-26 02:37:59 -05:00
op_helper.c	target/riscv: Fix implementation of HLVX.WU instruction	2021-03-08 14:40:28 -05:00
pmp.c	target/riscv: Change the TLB page size depends on PMP entries.	2021-03-08 12:46:27 -05:00
pmp.h	target/riscv: Change the TLB page size depends on PMP entries.	2021-03-08 12:46:27 -05:00
translate.c	target/riscv: Update the Hypervisor trap return/entry	2021-03-08 13:31:03 -05:00
unicorn.c	target/riscv: Add the virtulisation mode	2020-03-22 01:15:06 -04:00
unicorn.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
vector_helper.c	target/riscv/vector_helper: Fix build on 32-bit big endian hosts	2021-03-08 12:18:39 -05:00