Jim Wilson 30ab335bb3 RISC-V: Fixes to CSR_* register macros. ... This adds some missing CSR_* register macros, and documents some as being priv v1.9.1 specific. Backports commit 8e73df6aa3f2f0e5c26c03a94a88406616291815 from qemu		2019-03-19 23:39:49 -04:00
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insn_trans	target/riscv: Fix manually parsed 16 bit insn	2019-03-19 05:44:58 -04:00
cpu.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
cpu.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
cpu_bits.h	RISC-V: Fixes to CSR_* register macros.	2019-03-19 23:39:49 -04:00
cpu_helper.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
cpu_user.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
csr.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
fpu_helper.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
helper.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
insn16.decode	target/riscv: Convert quadrant 2 of RVXC insns to decodetree	2019-03-19 04:53:07 -04:00
insn32-64.decode	target/riscv: Convert RV64D insns to decodetree	2019-03-18 16:57:16 -04:00
insn32.decode	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	2019-03-19 05:17:54 -04:00
instmap.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
Makefile.objs	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	2019-03-19 04:45:53 -04:00
op_helper.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
pmp.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
pmp.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
translate.c	target/riscv: Remove decode_RV32_64G()	2019-03-19 05:37:42 -04:00
unicorn.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
unicorn.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00