Stefan Hajnoczi 320b59ddb9 qemu/atomic.h: rename atomic_ to qatomic_ ... clang's C11 atomic_fetch_*() functions only take a C11 atomic type pointer argument. QEMU uses direct types (int, etc) and this causes a compiler error when a QEMU code calls these functions in a source file that also included <stdatomic.h> via a system header file: $ CC=clang CXX=clang++ ./configure ... && make ../util/async.c:79:17: error: address argument to atomic operation must be a pointer to _Atomic type ('unsigned int *' invalid) Avoid using atomic_*() names in QEMU's atomic.h since that namespace is used by <stdatomic.h>. Prefix QEMU's APIs with 'q' so that atomic.h and <stdatomic.h> can co-exist. I checked /usr/include on my machine and searched GitHub for existing "qatomic_" users but there seem to be none. This patch was generated using: $ git grep -h -o '\<atomic\(64\)\?_[a-z0-9_]\+' include/qemu/atomic.h | \ sort -u >/tmp/changed_identifiers $ for identifier in $(</tmp/changed_identifiers); do sed -i "s%\<$identifier\>%q$identifier%g" \ $(git grep -I -l "\<$identifier\>") done I manually fixed line-wrap issues and misaligned rST tables. Backports d73415a315471ac0b127ed3fad45c8ec5d711de1		2021-03-08 14:34:35 -05:00
..
insn_trans	target/riscv: Support the Virtual Instruction fault	2021-03-08 13:55:02 -05:00
cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 19:35:46 -04:00
cpu.c	qemu/atomic.h: rename atomic_ to qatomic_	2021-03-08 14:34:35 -05:00
cpu.h	qemu/atomic.h: rename atomic_ to qatomic_	2021-03-08 14:34:35 -05:00
cpu_bits.h	target/riscv: Support the Virtual Instruction fault	2021-03-08 13:55:02 -05:00
cpu_helper.c	qemu/atomic.h: rename atomic_ to qatomic_	2021-03-08 14:34:35 -05:00
cpu_user.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
csr.c	qemu/atomic.h: rename atomic_ to qatomic_	2021-03-08 14:34:35 -05:00
fpu_helper.c	target/riscv: Check nanboxed inputs to fp helpers	2021-03-08 12:31:18 -05:00
helper.h	target/riscv: Support the Virtual Instruction fault	2021-03-08 13:55:02 -05:00
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-28 19:00:23 -04:00
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn32-64.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2021-03-08 13:13:32 -05:00
insn32.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2021-03-08 13:13:32 -05:00
instmap.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
internals.h	target/riscv: Check nanboxed inputs to fp helpers	2021-03-08 12:31:18 -05:00
Makefile.objs	target/riscv: add vector configure instruction	2021-02-26 02:37:59 -05:00
op_helper.c	target/riscv: Support the Virtual Instruction fault	2021-03-08 13:55:02 -05:00
pmp.c	target/riscv: Change the TLB page size depends on PMP entries.	2021-03-08 12:46:27 -05:00
pmp.h	target/riscv: Change the TLB page size depends on PMP entries.	2021-03-08 12:46:27 -05:00
translate.c	target/riscv: Update the Hypervisor trap return/entry	2021-03-08 13:31:03 -05:00
unicorn.c	target/riscv: Add the virtulisation mode	2020-03-22 01:15:06 -04:00
unicorn.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
vector_helper.c	target/riscv/vector_helper: Fix build on 32-bit big endian hosts	2021-03-08 12:18:39 -05:00