Peter Maydell 3619f707a6 target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry ... On 32-bit exception entry, CPSR.J must always be set to 0 (see v7A Arm ARM DDI0406C.c B1.8.5). CPSR.IL must also be cleared on 32-bit exception entry (see v8A Arm ARM DDI0487C.a G1.10). Clear these bits. (This fixes a bug which will never be noticed by non-buggy guests.) Backports commit 829f9fd394ab082753308cbda165c13eaf8fae49 from qemu		2018-08-25 04:28:22 -04:00
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arm	target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry	2018-08-25 04:28:22 -04:00
i386	target/i386: update MPX flags when CPL changes	2018-08-25 03:32:22 -04:00
m68k	target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn	2018-06-15 11:40:18 -04:00
mips	target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0	2018-08-17 14:25:22 -04:00
sparc	tcg: Pass tb and index to tcg_gen_exit_tb separately	2018-06-07 11:56:32 -04:00