Richard Henderson 4ef4735cd3 target/arm: Introduce PREDDESC field definitions ... SVE predicate operations cannot use the "usual" simd_desc encoding, because the lengths are not a multiple of 8. But we were abusing the SIMD_* fields to store values anyway. This abuse broke when SIMD_OPRSZ_BITS was modified in e2e7168a214. Introduce a new set of field definitions for exclusive use of predicates, so that it is obvious what kind of predicate we are manipulating. To be used in future patches Backports b64ee454a4a086ed459bcda4c0bbb54e197841e4		2021-03-04 15:08:32 -05:00
..
a32-uncond.decode	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
a32.decode	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
arm-powerctl.c	arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on()	2020-01-07 18:10:29 -05:00
arm-powerctl.h	ARM: Factor out ARM on/off PSCI control functions	2018-03-01 23:31:47 -05:00
arm_ldst.h	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
cpu-param.h	target/arm: Don't use a TLB for ARMMMUIdx_Stage2	2020-05-07 08:40:06 -04:00
cpu-qom.h	arm: Fix typo in AARCH64_CPU_GET_CLASS definition	2021-03-01 18:03:29 -05:00
cpu.c	target/arm: Implement SCR_EL2.EEL2	2021-03-04 15:03:08 -05:00
cpu.h	target/arm: Implement SCR_EL2.EEL2	2021-03-04 15:03:08 -05:00
cpu64.c	target/arm: enable Secure EL2 in max CPU	2021-03-04 15:04:43 -05:00
crypto_helper.c	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
debug_helper.c	target/arm: Stop assuming DBGDIDR always exists	2020-03-21 18:26:24 -04:00
helper-a64.c	target/arm: use arm_is_el2_enabled() where applicable	2021-03-04 13:49:19 -05:00
helper-a64.h	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
helper-sve.h	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
helper.c	target/arm: refactor vae1_tlbmask()	2021-03-04 15:05:54 -05:00
helper.h	target/arm: Fix neon VTBL/VTBX for len > 1	2021-03-02 13:23:13 -05:00
internals.h	target/arm: Introduce PREDDESC field definitions	2021-03-04 15:08:32 -05:00
iwmmxt_helper.c	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
kvm-consts.h	arm: better stub version for MISMATCH_CHECK	2018-03-02 00:13:45 -05:00
m-nocp.decode	target/arm: Implement new v8.1M VLLDM and VLSTM encodings	2021-03-03 19:01:33 -05:00
m_helper.c	target/arm: Implement CCR_S.TRD behaviour for SG insns	2021-03-03 19:05:25 -05:00
Makefile.objs	target/arm: Do M-profile NOCP checks early and via decodetree	2021-02-26 11:17:23 -05:00
mte_helper.c	target/arm: Fix reported EL for mte_check_fail	2021-03-01 20:10:44 -05:00
neon-dp.decode	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
neon-ls.decode	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
neon-shared.decode	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
neon_helper.c	target/arm: Convert Neon VADD, VSUB, VABD 3-reg-same insns to decodetree	2020-05-15 23:26:51 -04:00
op_addsub.h	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
op_helper.c	target/arm: add 64-bit S-EL2 to EL exception table	2021-03-04 14:00:23 -05:00
pauth_helper.c	target/arm: Implement an IMPDEF pauth algorithm	2021-03-04 13:38:22 -05:00
psci.c	fix WFI/WFE length in syndrome register	2018-03-05 11:21:51 -05:00
sve.decode	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
sve_helper.c	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
t16.decode	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
t32.decode	target/arm: Implement M-profile "minimal RAS implementation"	2021-03-03 19:07:27 -05:00
tlb_helper.c	target/arm: set HPFAR_EL2.NS on secure stage 2 faults	2021-03-04 14:54:33 -05:00
translate-a64.c	target/arm: add MMU stage 1 for Secure EL2	2021-03-04 14:16:31 -05:00
translate-a64.h	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
translate-neon.inc.c	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
translate-sve.c	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
translate-vfp.inc.c	target/arm: Implement FPCXT_NS fp system register	2021-03-03 20:02:36 -05:00
translate.c	target/arm: Implement SCR_EL2.EEL2	2021-03-04 15:03:08 -05:00
translate.h	target/arm: Rearrange {sve,fp}_check_access assert	2021-02-26 13:56:27 -05:00
unicorn.h	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
unicorn_aarch64.c	unicorn_aarch64: Use aa64_vfp_qreg instead of aa32_vfp_dreg	2018-09-03 07:47:40 +01:00
unicorn_arm.c	arm/translate: Do not tracecode when in an IT block	2021-02-07 19:14:32 +00:00
vec_helper.c	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
vec_internal.h	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
vfp-uncond.decode	arm tcg cpus: Fix Lesser GPL version number	2021-03-02 13:30:35 -05:00
vfp.decode	target/arm: Implement VLDR/VSTR system register	2021-03-03 18:42:05 -05:00
vfp_helper.c	target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension	2021-03-01 20:36:02 -05:00