Peter Maydell 524b54bc7b target/arm: Convert Neon 3-same-fp size field to MO_* in decode ... In the Neon instructions, some instruction formats have a 2-bit size field which corresponds exactly to QEMU's MO_8/16/32/64. However the floating-point insns in the 3-same group have a 1-bit size field which is "0 for 32-bit float and 1 for 16-bit float". Currently we pass these values directly through to trans_ functions, which means that when reading a particular trans_ function you need to know if that insn uses a 2-bit size or a 1-bit size. Move the handling of the 1-bit size to the decodetree file, so that all these insns consistently pass a size to the trans_ function which is an MO_8/16/32/64 value. In this commit we switch over the insns using the 3same_fp and 3same_fp_q0 formats. Backports commit 6cf0f240e0b980a877abed12d2995f740eae6515		2021-03-01 18:15:18 -05:00
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arm	target/arm: Convert Neon 3-same-fp size field to MO_* in decode	2021-03-01 18:15:18 -05:00
i386	target/i386: floatx80: avoid compound literals in static initializers	2021-02-25 23:38:54 -05:00
m68k	target/m68k: consolidate physical translation offset into get_physical_address()	2021-02-25 23:13:48 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: vector single-width integer multiply instructions	2021-02-26 10:46:26 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00