Palmer Dabbelt 5b59f956b3 RISC-V: Add support for the Zifencei extension ... fence.i has been split out of the base ISA as part of the ratification process. This patch adds a Zifencei argument, which disables the fence.i instruction. Backports commit 50fba816cd226001bec3e495c39879deb2fa5432 from qemu		2019-08-08 17:09:09 -04:00
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trans_privileged.inc.c	target/riscv: Add the privledge spec version 1.11.0	2019-08-08 17:03:33 -04:00
trans_rva.inc.c	target/riscv: Convert RV64A insns to decodetree	2019-03-18 16:27:53 -04:00
trans_rvd.inc.c	target/riscv: Convert RV64D insns to decodetree	2019-03-18 16:57:16 -04:00
trans_rvf.inc.c	target/riscv: Convert RV64F insns to decodetree	2019-03-18 16:43:17 -04:00
trans_rvi.inc.c	RISC-V: Add support for the Zifencei extension	2019-08-08 17:09:09 -04:00
trans_rvm.inc.c	target/riscv: Zero extend the inputs of divuw and remuw	2019-03-26 20:38:17 -04:00