Yongbok Kim 6212fb2dc7 target-mips: fix updating XContext on mmu exception ... Correct updating XContext.Region field on mmu exceptions. If Config3.CTXTC = 0 then the R field of XContext has to be updated with the value of bits 63..62 of the virtual address upon a TLB exception. Also fixed the below line which overs 80 characters. Backports commit 60270f85cc93d2d34e45b7679c374b1d771f0eeb from qemu		2018-02-17 15:24:14 -05:00
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cpu-qom.h	remove slow cpu QOM casts (#815)	2017-05-02 14:56:39 +08:00
cpu.c	target-mips: implement the CPU wake-up on non-enabled interrupts in R6	2018-02-17 15:24:12 -05:00
cpu.h	target-mips: add PC, XNP reg numbers to RDHWR	2018-02-17 15:24:13 -05:00
dsp_helper.c	Added MIPS support and projects for all samples.	2017-01-23 01:05:08 +11:00
helper.c	target-mips: fix updating XContext on mmu exception	2018-02-17 15:24:14 -05:00
helper.h	target-mips: add PC, XNP reg numbers to RDHWR	2018-02-17 15:24:13 -05:00
lmi_helper.c	import	2015-08-21 15:04:50 +08:00
Makefile.objs	import	2015-08-21 15:04:50 +08:00
mips-defs.h	target-mips: fix MIPS64R6-generic configuration	2018-02-17 15:23:21 -05:00
msa_helper.c	target-mips: improve exception handling	2018-02-17 15:23:53 -05:00
op_helper.c	target-mips: add PC, XNP reg numbers to RDHWR	2018-02-17 15:24:13 -05:00
TODO	import	2015-08-21 15:04:50 +08:00
translate.c	target-mips: add SIGRIE instruction	2018-02-17 15:24:13 -05:00
translate_init.c	target-mips: Set Config5.XNP for R6 cores	2018-02-17 15:24:13 -05:00
unicorn.c	Merge branch 'master' into msvc2	2017-04-21 01:17:00 +08:00
unicorn.h	armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition.	2017-03-15 22:25:35 +08:00