unicorn/qemu/target/riscv/insn_trans
LIU Zhiwei 7d0d7338c2 target/riscv: add vector amo operations
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction

Backports 268fcca66bde62257960ec8d859de374315a5e3d
2021-02-26 09:47:32 -05:00
..
trans_privileged.inc.c target/riscv: Move the hfence instructions to the rvh decode 2021-02-25 11:59:49 -05:00
trans_rva.inc.c tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
trans_rvd.inc.c target/riscv: fsd/fsw doesn't dirty FP state 2020-03-21 12:20:52 -04:00
trans_rvf.inc.c riscv: Add helper to make NaN-boxing for FP register 2021-02-25 11:53:27 -05:00
trans_rvh.inc.c target/riscv: Implement checks for hfence 2021-02-25 12:03:57 -05:00
trans_rvi.inc.c tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
trans_rvm.inc.c target/riscv: Zero extend the inputs of divuw and remuw 2019-03-26 20:38:17 -04:00
trans_rvv.inc.c target/riscv: add vector amo operations 2021-02-26 09:47:32 -05:00