Peter Maydell 82ce9221a0 target/arm: Make number of counters in PMCR follow the CPU ... Currently we give all the v7-and-up CPUs a PMU with 4 counters. This means that we don't provide the 6 counters that are required by the Arm BSA (Base System Architecture) specification if the CPU supports the Virtualization extensions. Instead of having a single PMCR_NUM_COUNTERS, make each CPU type specify the PMCR reset value (obtained from the appropriate TRM), and use the 'N' field of that value to define the number of counters provided. This means that we now supply 6 counters for Cortex-A53, A57, A72, A15 and A9 as well as '-cpu max'; Cortex-A7 and A8 stay at 4; and Cortex-R5 goes down to 3. Note that because we now use the PMCR reset value of the specific implementation, we no longer set the LC bit out of reset. This has an UNKNOWN value out of reset for all cores with any AArch32 support, so guest software should be setting it anyway if it wants it. Backports f7fb73b8cdd3f77e26f9fcff8cf24ff1b58d200f		2021-03-30 15:30:31 -04:00
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arm	target/arm: Make number of counters in PMCR follow the CPU	2021-03-30 15:30:31 -04:00
i386	qemu/atomic.h: rename atomic_ to qatomic_	2021-03-08 14:34:35 -05:00
m68k	target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature	2021-03-12 14:55:43 -05:00
mips	mips: Fix build	2021-03-05 08:51:51 -05:00
riscv	target/riscv: Prevent lost illegal instruction exceptions	2021-03-30 15:23:00 -04:00
sparc	sparc: Fix build	2021-03-05 08:54:43 -05:00