unicorn/qemu/target-mips
James Hogan 8689c6efef
target-mips: Fix exceptions while UX=0
Commit 01f728857941 ("target-mips: Status.UX/SX/KX enable 32-bit address
wrapping") added a new hflag MIPS_HFLAG_AWRAP, which indicates that
64-bit addressing is disallowed in the current mode, so hflag users
don't need to worry about the complexities of working that out, for
example checking both MIPS_HFLAG_KSU and MIPS_HFLAG_UX.

However when exceptions are taken outside of exception level,
mips_cpu_do_interrupt() manipulates the env->hflags directly rather than
using compute_hflags() to update them, and this code wasn't updated
accordingly. As a result, when UX is cleared, MIPS_HFLAG_AWRAP is set,
but it doesn't get cleared on entry back into kernel mode due to an
exception. Kernel mode then cannot access the 64-bit segments resulting
in a nested exception loop. The same applies to errors and debug
exceptions.

Fix by updating mips_cpu_do_interrupt() to clear the MIPS_HFLAG_WRAP
flag when necessary, according to compute_hflags().

Backports commit 7871abb94c2f4adc39f2487f6edf5e69ba872a65 from qemu
2018-02-17 18:57:52 -05:00
..
cpu-qom.h remove slow cpu QOM casts (#815) 2017-05-02 14:56:39 +08:00
cpu.c target-mips: implement the CPU wake-up on non-enabled interrupts in R6 2018-02-17 15:24:12 -05:00
cpu.h target-mips: add PC, XNP reg numbers to RDHWR 2018-02-17 15:24:13 -05:00
dsp_helper.c Added MIPS support and projects for all samples. 2017-01-23 01:05:08 +11:00
helper.c target-mips: Fix exceptions while UX=0 2018-02-17 18:57:52 -05:00
helper.h target-mips: add PC, XNP reg numbers to RDHWR 2018-02-17 15:24:13 -05:00
lmi_helper.c import 2015-08-21 15:04:50 +08:00
Makefile.objs import 2015-08-21 15:04:50 +08:00
mips-defs.h target-mips: fix MIPS64R6-generic configuration 2018-02-17 15:23:21 -05:00
msa_helper.c target-mips: improve exception handling 2018-02-17 15:23:53 -05:00
op_helper.c target-mips: add PC, XNP reg numbers to RDHWR 2018-02-17 15:24:13 -05:00
TODO import 2015-08-21 15:04:50 +08:00
translate.c target-mips: add SIGRIE instruction 2018-02-17 15:24:13 -05:00
translate_init.c target-mips: Set Config5.XNP for R6 cores 2018-02-17 15:24:13 -05:00
unicorn.c Merge branch 'master' into msvc2 2017-04-21 01:17:00 +08:00
unicorn.h armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition. 2017-03-15 22:25:35 +08:00