unicorn/qemu/target
Peter Maydell 8d34a271f6
target/arm: Implement tailchaining for M profile cores
Tailchaining is an optimization in handling of exception return
for M-profile cores: if we are about to pop the exception stack
for an exception return, but there is a pending exception which
is higher priority than the priority we are returning to, then
instead of unstacking and then immediately taking the exception
and stacking registers again, we can chain to the pending
exception without unstacking and stacking.

For v6M and v7M it is IMPDEF whether tailchaining happens for pending
exceptions; for v8M this is architecturally required. Implement it
in QEMU for all M-profile cores, since in practice v6M and v7M
hardware implementations generally do have it.

(We were already doing tailchaining for derived exceptions which
happened during exception return, like the validity checks and
stack access failures; these have always been required to be
tailchained for all versions of the architecture.)

Backports commit 5f62d3b9e67bfc3deb970e3c7fb7df7e57d46fc3 from qemu
2018-08-16 07:03:51 -04:00
..
arm target/arm: Implement tailchaining for M profile cores 2018-08-16 07:03:51 -04:00
i386 i386: implement MSR_SMI_COUNT for TCG 2018-08-02 21:27:08 -04:00
m68k target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn 2018-06-15 11:40:18 -04:00
mips target/mips: Fix data type for offset 2018-07-03 01:01:09 -04:00
sparc tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-07 11:56:32 -04:00