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unicorn/qemu/target/riscv/insn_trans
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Bastian Koppelmann c0f036578c
target/riscv: Fix manually parsed 16 bit insn 
during the refactor to decodetree we removed the manual decoding that is
necessary for c.jal/c.addiw and removed the translation of c.flw/c.ld
and c.fsw/c.sd. This reintroduces the manual parsing and the
omited implementation.

Backports commit f330433b3633647b047cfa418c2ca4d18fda69c7 from qemu
2019-03-19 05:44:58 -04:00
..
trans_privileged.inc.c target/riscv: Convert RV priv insns to decodetree 2019-03-19 04:40:24 -04:00
trans_rva.inc.c target/riscv: Convert RV64A insns to decodetree 2019-03-18 16:27:53 -04:00
trans_rvc.inc.c target/riscv: Fix manually parsed 16 bit insn 2019-03-19 05:44:58 -04:00
trans_rvd.inc.c target/riscv: Convert RV64D insns to decodetree 2019-03-18 16:57:16 -04:00
trans_rvf.inc.c target/riscv: Convert RV64F insns to decodetree 2019-03-18 16:43:17 -04:00
trans_rvi.inc.c target/riscv: Rename trans_arith to gen_arith 2019-03-19 05:35:44 -04:00
trans_rvm.inc.c target/riscv: Rename trans_arith to gen_arith 2019-03-19 05:35:44 -04:00