Michael Clark 8ffa68e757 RISC-V: Change local interrupts from edge to level ... This effectively changes riscv_cpu_update_mip from edge to level. i.e. cpu_interrupt or cpu_reset_interrupt are called regardless of the current interrupt level. Fixes WFI doesn't return when a IPI is issued: - https://github.com/riscv/riscv-qemu/issues/132 To test: 1) Apply RISC-V Linux CPU hotplug patch: - http://lists.infradead.org/pipermail/linux-riscv/2018-May/000603.html 2) Enable CONFIG_CPU_HOTPLUG in linux .config 3) Try to offline and online cpus: echo 1 > /sys/devices/system/cpu/cpu2/online echo 0 > /sys/devices/system/cpu/cpu2/online echo 1 > /sys/devices/system/cpu/cpu2/online Backports commit d26f5a423438e579d3ff0ca35e44edb966a36233 from qemu		2019-03-19 23:58:31 -04:00
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insn_trans	target/riscv: Fix manually parsed 16 bit insn	2019-03-19 05:44:58 -04:00
cpu.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
cpu.h	RISC-V: linux-user support for RVE ABI	2019-03-19 23:58:31 -04:00
cpu_bits.h	RISC-V: Fixes to CSR_* register macros.	2019-03-19 23:39:49 -04:00
cpu_helper.c	RISC-V: Change local interrupts from edge to level	2019-03-19 23:58:31 -04:00
cpu_user.h	RISC-V: linux-user support for RVE ABI	2019-03-19 23:58:31 -04:00
csr.c	RISC-V: Allow interrupt controllers to claim interrupts	2019-03-19 23:48:12 -04:00
fpu_helper.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
helper.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
insn16.decode	target/riscv: Convert quadrant 2 of RVXC insns to decodetree	2019-03-19 04:53:07 -04:00
insn32-64.decode	target/riscv: Convert RV64D insns to decodetree	2019-03-18 16:57:16 -04:00
insn32.decode	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	2019-03-19 05:17:54 -04:00
instmap.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
Makefile.objs	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	2019-03-19 04:45:53 -04:00
op_helper.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
pmp.c	riscv: pmp: Log pmp access errors as guest errors	2019-03-19 23:45:03 -04:00
pmp.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
translate.c	target/riscv: Remove decode_RV32_64G()	2019-03-19 05:37:42 -04:00
unicorn.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
unicorn.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00