Fredrik Noring 93fb8273c8 target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants ... The R5900 implements the 64-bit MIPS III instruction set except DMULT, DMULTU, DDIV, DDIVU, LL, SC, LLD and SCD. The MIPS IV instructions MOVN, MOVZ and PREF are implemented. It has the R5900-specific three-operand instructions MADD, MADDU, MULT and MULTU as well as pipeline 1 versions MULT1, MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1. A set of 93 128-bit multimedia instructions specific to the R5900 is also implemented. The Toshiba TX System RISC TX79 Core Architecture manual: https://wiki.qemu.org/File:C790.pdf describes the C790 processor that is a follow-up to the R5900. There are a few notable differences in that the R5900 FPU - is not IEEE 754-1985 compliant, - does not implement double format, and - its machine code is nonstandard. Backports commit 6f692818a7b53630702d25a709cd61282fd139ad from qemu		2018-11-10 11:29:25 -05:00
..
arm	target/arm: Only flush tlb if ASID changes	2018-11-10 11:26:24 -05:00
i386	target/i386: Convert to HAVE_CMPXCHG128	2018-10-23 15:21:03 -04:00
m68k	Removes accessible assert	2018-10-06 05:02:20 -04:00
mips	target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants	2018-11-10 11:29:25 -05:00
sparc	Sparc increase ttl number	2018-10-06 04:55:52 -04:00