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The R5900 implements the 64-bit MIPS III instruction set except DMULT, DMULTU, DDIV, DDIVU, LL, SC, LLD and SCD. The MIPS IV instructions MOVN, MOVZ and PREF are implemented. It has the R5900-specific three-operand instructions MADD, MADDU, MULT and MULTU as well as pipeline 1 versions MULT1, MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1. A set of 93 128-bit multimedia instructions specific to the R5900 is also implemented. The Toshiba TX System RISC TX79 Core Architecture manual: https://wiki.qemu.org/File:C790.pdf describes the C790 processor that is a follow-up to the R5900. There are a few notable differences in that the R5900 FPU - is not IEEE 754-1985 compliant, - does not implement double format, and - its machine code is nonstandard. Backports commit 6f692818a7b53630702d25a709cd61282fd139ad from qemu |
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cp0_timer.c | ||
cpu-qom.h | ||
cpu.c | ||
cpu.h | ||
dsp_helper.c | ||
helper.c | ||
helper.h | ||
internal.h | ||
lmi_helper.c | ||
Makefile.objs | ||
mips-defs.h | ||
msa_helper.c | ||
op_helper.c | ||
TODO | ||
translate.c | ||
translate_init.c | ||
unicorn.c | ||
unicorn.h |