James Hogan 987401c4d4 target-mips: Don't stop on [d]mtc0 DESAVE/KScratch ... Writing to the MIPS DESAVE register (and now the KScratch registers) will stop translation, supposedly due to risk of execution mode switches. However these registers are basically RW scratch registers with no side effects so there is no risk of them triggering execution mode changes. Drop the bstate = BS_STOP for these registers for both mtc0 and dmtc0. Backports commit cb539fd241900f51de7d21244f7a55422ad0d40a from qemu		2018-03-04 01:25:27 -05:00
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cpu-qom.h	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
cpu.c	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
cpu.h	target/mips: Add segmentation control registers	2018-03-04 01:00:42 -05:00
dsp_helper.c	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
helper.c	target/mips: Implement segmentation control	2018-03-04 01:06:13 -05:00
helper.h	target/mips: Add segmentation control registers	2018-03-04 01:00:42 -05:00
lmi_helper.c	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
Makefile.objs	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
mips-defs.h	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
msa_helper.c	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
op_helper.c	target/mips: Add segmentation control registers	2018-03-04 01:00:42 -05:00
TODO	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
translate.c	target-mips: Don't stop on [d]mtc0 DESAVE/KScratch	2018-03-04 01:25:27 -05:00
translate_init.c	target/mips: Enable CP0_EBase.WG on MIPS64 CPUs	2018-03-04 01:09:47 -05:00
unicorn.c	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
unicorn.h	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00