unicorn/qemu/target/riscv
Richard Henderson 9c1212f627
target/riscv: Remove spaces from register names
These extra spaces make the "-d op" dump look weird.

Backports commit 7f9188e210aff6522a960d9669a583a3a752ddc0 from qemu
2019-05-28 19:08:50 -04:00
..
insn_trans target/riscv: Split gen_arith_imm into functional and temp 2019-05-28 19:07:53 -04:00
cpu.c target/riscv: Remove spaces from register names 2019-05-28 19:08:50 -04:00
cpu.h target/riscv: Convert to CPUClass::tlb_fill 2019-05-16 17:24:01 -04:00
cpu_bits.h RISC-V: Fixes to CSR_* register macros. 2019-03-19 23:39:49 -04:00
cpu_helper.c tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-16 17:35:37 -04:00
cpu_user.h RISC-V: linux-user support for RVE ABI 2019-03-19 23:58:31 -04:00
csr.c RISC-V: Add support for vectored interrupts 2019-03-19 23:58:31 -04:00
fpu_helper.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
helper.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
insn16-32.decode target/riscv: Split RVC32 and RVC64 insns into separate files 2019-05-28 19:00:23 -04:00
insn16-64.decode target/riscv: Split RVC32 and RVC64 insns into separate files 2019-05-28 19:00:23 -04:00
insn16.decode target/riscv: Split RVC32 and RVC64 insns into separate files 2019-05-28 19:00:23 -04:00
insn32-64.decode target/riscv: Convert RV64D insns to decodetree 2019-03-18 16:57:16 -04:00
insn32.decode target/riscv: Name the argument sets for all of insn32 formats 2019-05-28 18:36:53 -04:00
instmap.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
Makefile.objs target/riscv: Split RVC32 and RVC64 insns into separate files 2019-05-28 19:00:23 -04:00
op_helper.c target/riscv: Do not allow sfence.vma from user mode 2019-05-28 18:29:46 -04:00
pmp.c riscv: pmp: Log pmp access errors as guest errors 2019-03-19 23:45:03 -04:00
pmp.h Clean up ill-advised or unusual header guards 2019-05-14 08:02:53 -04:00
translate.c target/riscv: Split gen_arith_imm into functional and temp 2019-05-28 19:07:53 -04:00
unicorn.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
unicorn.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00