Lioncash b6f752970b target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.		2019-03-08 21:46:10 -05:00
..
crypto	Drop unused crypto source files	2018-02-17 15:23:57 -05:00
exec	include/exec/helper-head.h: support "const void *" in helper calls	2019-02-22 19:12:09 -05:00
fpu	softfloat: Implement float128_to_uint32	2019-02-28 15:13:09 -05:00
hw	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
qapi	qapi: Rewrite string-input-visitor's integer and list parsing	2018-12-18 04:57:25 -05:00
qemu	tcg: add early clober modifier in atomic16_cmpxchg on aarch64	2019-02-07 08:58:53 -05:00
qom	arm: Clarify the logic of set_pc()	2019-02-03 17:55:30 -05:00
sysemu	tcg: add options for enabling MTTCG	2018-03-02 09:25:01 -05:00
config.h	import	2015-08-21 15:04:50 +08:00
elf.h	include/elf: Update elf.h to commit f71a8eaffba3271cf7cdad95572f6996f7523a5b	2018-03-11 15:34:35 -04:00
glib_compat.h	target/arm: expose remaining CPUID registers as RAZ	2019-02-15 17:48:37 -05:00
qemu-common.h	tcg: Add EXCP_ATOMIC	2018-02-27 11:57:58 -05:00