Lioncash b6f752970b target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.		2019-03-08 21:46:10 -05:00
..
accel	cputlb: update TLB entry/index after tlb_fill	2019-02-12 11:48:48 -05:00
crypto	crypto: Clean up includes	2018-02-19 00:47:40 -05:00
default-configs	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
docs	docs/devel/memory.txt: Document _with_attrs accessors	2018-10-04 04:46:26 -04:00
fpu	softfloat: Support float_round_to_odd more places	2019-02-28 15:17:38 -05:00
hw	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
include	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
qapi	qapi: Rewrite string-input-visitor's integer and list parsing	2018-12-18 04:57:25 -05:00
qobject	qstring: Move qstring_from_substr()'s @end one to the right	2018-08-02 21:24:19 -04:00
qom	qom/cpu: Add cluster_index to CPUState	2019-01-30 12:59:59 -05:00
scripts	qapi: Prepare for system modules other than 'builtin'	2019-02-21 09:58:54 -05:00
target	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
tcg	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
util	mmap-alloc: fix hugetlbfs misaligned length in ppc64	2019-02-05 16:52:39 -05:00
aarch64.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
aarch64eb.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
accel.c	clean-up: removed duplicate #includes	2018-02-28 08:51:56 -05:00
arm.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
armeb.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
CODING_STYLE
configure	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
COPYING
COPYING.LIB
cpus.c	Include qapi/error.h exactly where needed	2018-03-07 12:26:38 -05:00
exec.c	exec.c: Use correct attrs in cpu_memory_rw_debug()	2019-01-29 17:05:50 -05:00
gen_all_header.sh
glib_compat.c	target/arm: expose remaining CPUID registers as RAZ	2019-02-15 17:48:37 -05:00
HACKING	HACKING: document preference for g_new instead of g_malloc	2018-05-22 00:30:50 -04:00
header_gen.py	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
ioport.c	hw: remove pio_addr_t	2018-02-24 02:43:16 -05:00
LICENSE
m68k.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
Makefile	Revert "Makefile: Rename TARGET_DIRS to TARGET_LIST"	2018-07-05 17:40:24 -04:00
Makefile.objs	qapi: Move qapi-schema.json to qapi/, rename generated files	2018-03-09 11:35:11 -05:00
Makefile.target	configure: Remove old -fno-gcse workaround for GCC 4.6.x and 4.7.[012]	2018-12-18 03:52:36 -05:00
memory.c	memory: learn about non-volatile memory region	2018-11-11 08:50:39 -05:00
memory_ldst.inc.c	exec: Fix MAP_RAM for cached access	2018-07-03 01:11:12 -04:00
memory_mapping.c	include/qemu/osdep.h: Don't include qapi/error.h	2018-02-21 23:08:18 -05:00
mips.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
mips64.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
mips64el.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
mipsel.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
powerpc.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
qemu-timer.c	timer/cpus: fix some typos and update some comments	2018-02-25 23:21:57 -05:00
riscv32.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
riscv64.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
rules.mak	build-sys: silence make by default or V=0	2018-03-06 08:58:03 -05:00
sparc.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
sparc64.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
unicorn_common.h	unicorn_common: Fix unicorn memory functions failing	2018-09-03 10:40:14 -04:00
VERSION	Open 4.0 development tree	2018-12-11 20:33:45 -05:00
vl.c	Use cpu_create(type) instead of cpu_init(cpu_model)	2018-03-20 14:20:30 -04:00
vl.h
x86_64.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00