Richard Henderson fbf91a6535 cpu: Replace ENV_GET_CPU with env_cpu ... Now that we have both ArchCPU and CPUArchState, we can define this generically instead of via macro in each target's cpu.h. Backports commit 29a0af618ddd21f55df5753c3e16b0625f534b3c from qemu		2019-06-12 11:16:16 -04:00
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insn_trans	target/riscv: Split gen_arith_imm into functional and temp	2019-05-28 19:07:53 -04:00
cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 19:35:46 -04:00
cpu.c	target/riscv: Add a base 32 and 64 bit CPU	2019-05-28 19:11:12 -04:00
cpu.h	cpu: Replace ENV_GET_CPU with env_cpu	2019-06-12 11:16:16 -04:00
cpu_bits.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
cpu_helper.c	target/riscv: Improve the scause logic	2019-05-28 19:14:44 -04:00
cpu_user.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
csr.c	target/riscv: Only flush TLB if SATP.ASID changes	2019-05-28 19:22:51 -04:00
fpu_helper.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
helper.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-28 19:00:23 -04:00
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn32-64.decode	target/riscv: Convert RV64D insns to decodetree	2019-03-18 16:57:16 -04:00
insn32.decode	target/riscv: Name the argument sets for all of insn32 formats	2019-05-28 18:36:53 -04:00
instmap.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
Makefile.objs	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-28 19:00:23 -04:00
op_helper.c	target/riscv: Do not allow sfence.vma from user mode	2019-05-28 18:29:46 -04:00
pmp.c	riscv: pmp: Log pmp access errors as guest errors	2019-03-19 23:45:03 -04:00
pmp.h	Clean up ill-advised or unusual header guards	2019-05-14 08:02:53 -04:00
translate.c	target/riscv: Split gen_arith_imm into functional and temp	2019-05-28 19:07:53 -04:00
unicorn.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
unicorn.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00