Richard Henderson c387d51c1d target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half ... We were using the wrong flush-to-zero bit for the non-half input. Fixes: 46d33d1e3c9 Backports commit e4ab5124a5c2e2291006b24bdc21c3dd8d087ff4 from qemu		2018-08-17 14:05:10 -04:00
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arm	target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half	2018-08-17 14:05:10 -04:00
i386	i386: implement MSR_SMI_COUNT for TCG	2018-08-02 21:27:08 -04:00
m68k	target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn	2018-06-15 11:40:18 -04:00
mips	target/mips: Fix data type for offset	2018-07-03 01:01:09 -04:00
sparc	tcg: Pass tb and index to tcg_gen_exit_tb separately	2018-06-07 11:56:32 -04:00