Alexandre Mergnat cd956f5aa6 target/riscv: Fix pmp NA4 implementation ... The end address calculation for NA4 mode is wrong because the address used isn't shifted. It doesn't watch 4 bytes but a huge range because the end address calculation is wrong. The solution is to use the shifted address calculated for start address variable. Modifications are tested on Zephyr OS userspace test suite which works for other RISC-V boards (E31 and E34 core). Backports cfad709bceb629a4ebeb5d8a3acd1871b9a6436b		2021-03-08 12:14:51 -05:00
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accel
crypto
default-configs
docs
fpu	softfloat: Define misc operations for bfloat16	2021-02-27 16:41:46 -05:00
hw
include
qapi
qobject
qom
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target	target/riscv: Fix pmp NA4 implementation	2021-03-08 12:14:51 -05:00
tcg
util
aarch64.h	target/arm: Speed up aarch64 TBL/TBX	2021-03-08 11:31:24 -05:00
aarch64eb.h	target/arm: Speed up aarch64 TBL/TBX	2021-03-08 11:31:24 -05:00
accel.c
arm.h
armeb.h
CODING_STYLE.rst
configure
COPYING
COPYING.LIB
cpus.c
exec.c
gen_all_header.sh
glib_compat.c
header_gen.py	target/arm: Speed up aarch64 TBL/TBX	2021-03-08 11:31:24 -05:00
ioport.c
LICENSE
m68k.h
Makefile
Makefile.objs
Makefile.target
memory.c
memory_ldst.inc.c
memory_mapping.c
mips.h
mips64.h
mips64el.h
mipsel.h
powerpc.h
qemu-timer.c
riscv32.h	target/riscv: vector compress instruction	2021-03-07 12:47:46 -05:00
riscv64.h	target/riscv: vector compress instruction	2021-03-07 12:47:46 -05:00
rules.mak
sparc.h
sparc64.h
unicorn_common.h
VERSION
vl.c
vl.h
x86_64.h