Alexandre Mergnat cd956f5aa6 target/riscv: Fix pmp NA4 implementation ... The end address calculation for NA4 mode is wrong because the address used isn't shifted. It doesn't watch 4 bytes but a huge range because the end address calculation is wrong. The solution is to use the shifted address calculated for start address variable. Modifications are tested on Zephyr OS userspace test suite which works for other RISC-V boards (E31 and E34 core). Backports cfad709bceb629a4ebeb5d8a3acd1871b9a6436b		2021-03-08 12:14:51 -05:00
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arm	target/arm/cpu: Update coding style to make checkpatch.pl happy	2021-03-08 11:35:28 -05:00
i386	i386: Fix build	2021-03-05 08:35:14 -05:00
m68k	m68k: Fix build	2021-03-05 08:29:53 -05:00
mips	mips: Fix build	2021-03-05 08:51:51 -05:00
riscv	target/riscv: Fix pmp NA4 implementation	2021-03-08 12:14:51 -05:00
sparc	sparc: Fix build	2021-03-05 08:54:43 -05:00