Alexandre Mergnat cd956f5aa6 target/riscv: Fix pmp NA4 implementation ... The end address calculation for NA4 mode is wrong because the address used isn't shifted. It doesn't watch 4 bytes but a huge range because the end address calculation is wrong. The solution is to use the shifted address calculated for start address variable. Modifications are tested on Zephyr OS userspace test suite which works for other RISC-V boards (E31 and E34 core). Backports cfad709bceb629a4ebeb5d8a3acd1871b9a6436b		2021-03-08 12:14:51 -05:00
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insn_trans	target/riscv: fix return value of do_opivx_widen()	2021-03-08 12:13:16 -05:00
cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 19:35:46 -04:00
cpu.c	target/riscv: Enable vector extensions	2021-03-08 11:18:36 -05:00
cpu.h	target/riscv: fix vill bit index in vtype register	2021-03-08 12:13:58 -05:00
cpu_bits.h	target/riscv: support vector extension csr	2021-02-26 02:25:58 -05:00
cpu_helper.c	target/riscv: Report errors validating 2nd-stage PTEs	2021-02-25 11:55:53 -05:00
cpu_user.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
csr.c	target/riscv: support vector extension csr	2021-02-26 02:25:58 -05:00
fpu_helper.c	target/riscv: vector floating-point classify instructions	2021-03-07 11:55:45 -05:00
helper.h	target/riscv: vector compress instruction	2021-03-07 12:47:46 -05:00
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-28 19:00:23 -04:00
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
insn32-64.decode	target/riscv: add vector amo operations	2021-02-26 09:47:32 -05:00
insn32.decode	target/riscv: vector compress instruction	2021-03-07 12:47:46 -05:00
instmap.h	Supply missing header guards	2019-06-12 10:59:10 -04:00
internals.h	target/riscv: integer scalar move instruction	2021-03-07 12:38:41 -05:00
Makefile.objs	target/riscv: add vector configure instruction	2021-02-26 02:37:59 -05:00
op_helper.c	target/riscv: Implement checks for hfence	2021-02-25 12:03:57 -05:00
pmp.c	target/riscv: Fix pmp NA4 implementation	2021-03-08 12:14:51 -05:00
pmp.h	RISC-V: Check for the effective memory privilege mode during PMP checks	2019-08-08 16:52:57 -04:00
translate.c	target/riscv: add vector stride load and store instructions	2021-02-26 02:55:14 -05:00
unicorn.c	target/riscv: Add the virtulisation mode	2020-03-22 01:15:06 -04:00
unicorn.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
vector_helper.c	target/riscv: vector compress instruction	2021-03-07 12:47:46 -05:00