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387 lines
10 KiB
C
387 lines
10 KiB
C
/*
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* QEMU RISC-V PMP (Physical Memory Protection)
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*
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* Author: Daire McNamara, daire.mcnamara@emdalo.com
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* Ivan Griffin, ivan.griffin@emdalo.com
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*
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* This provides a RISC-V Physical Memory Protection implementation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* PMP (Physical Memory Protection) is as-of-yet unused and needs testing.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qemu-common.h"
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#ifndef CONFIG_USER_ONLY
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#define RISCV_DEBUG_PMP 0
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#define PMP_DEBUG(fmt, ...) \
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do { \
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if (RISCV_DEBUG_PMP) { \
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qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, ##__VA_ARGS__);\
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} \
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} while (0)
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static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
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uint8_t val);
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static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
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static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index);
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/*
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* Accessor method to extract address matching type 'a field' from cfg reg
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*/
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static inline uint8_t pmp_get_a_field(uint8_t cfg)
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{
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uint8_t a = cfg >> 3;
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return a & 0x3;
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}
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/*
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* Check whether a PMP is locked or not.
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*/
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static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
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{
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if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) {
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return 1;
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}
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/* Top PMP has no 'next' to check */
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if ((pmp_index + 1u) >= MAX_RISCV_PMPS) {
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return 0;
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}
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/* In TOR mode, need to check the lock bit of the next pmp
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* (if there is a next)
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*/
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const uint8_t a_field =
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pmp_get_a_field(env->pmp_state.pmp[pmp_index + 1].cfg_reg);
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if ((env->pmp_state.pmp[pmp_index + 1u].cfg_reg & PMP_LOCK) &&
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(PMP_AMATCH_TOR == a_field)) {
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return 1;
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}
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return 0;
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}
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/*
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* Count the number of active rules.
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*/
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static inline uint32_t pmp_get_num_rules(CPURISCVState *env)
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{
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return env->pmp_state.num_rules;
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}
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/*
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* Accessor to get the cfg reg for a specific PMP/HART
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*/
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static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
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{
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if (pmp_index < MAX_RISCV_PMPS) {
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return env->pmp_state.pmp[pmp_index].cfg_reg;
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}
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return 0;
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}
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/*
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* Accessor to set the cfg reg for a specific PMP/HART
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* Bounds checks and relevant lock bit.
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*/
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static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
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{
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if (pmp_index < MAX_RISCV_PMPS) {
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if (!pmp_is_locked(env, pmp_index)) {
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env->pmp_state.pmp[pmp_index].cfg_reg = val;
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pmp_update_rule(env, pmp_index);
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
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}
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"ignoring pmpcfg write - out of bounds\n");
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}
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}
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static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea)
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{
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/*
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aaaa...aaa0 8-byte NAPOT range
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aaaa...aa01 16-byte NAPOT range
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aaaa...a011 32-byte NAPOT range
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...
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aa01...1111 2^XLEN-byte NAPOT range
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a011...1111 2^(XLEN+1)-byte NAPOT range
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0111...1111 2^(XLEN+2)-byte NAPOT range
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1111...1111 Reserved
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*/
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if (a == -1) {
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*sa = 0u;
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*ea = -1;
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return;
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} else {
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target_ulong t1 = ctz64(~a);
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target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 2;
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target_ulong range = ((target_ulong)1 << (t1 + 3)) - 1;
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*sa = base;
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*ea = base + range;
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}
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}
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/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
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* end address values.
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* This function is called relatively infrequently whereas the check that
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* an address is within a pmp rule is called often, so optimise that one
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*/
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static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
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{
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int i;
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env->pmp_state.num_rules = 0;
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uint8_t this_cfg = env->pmp_state.pmp[pmp_index].cfg_reg;
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target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg;
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target_ulong prev_addr = 0u;
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target_ulong sa = 0u;
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target_ulong ea = 0u;
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if (pmp_index >= 1u) {
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prev_addr = env->pmp_state.pmp[pmp_index - 1].addr_reg;
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}
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switch (pmp_get_a_field(this_cfg)) {
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case PMP_AMATCH_OFF:
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sa = 0u;
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ea = -1;
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break;
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case PMP_AMATCH_TOR:
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sa = prev_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
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ea = (this_addr << 2) - 1u;
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break;
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case PMP_AMATCH_NA4:
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sa = this_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
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ea = (this_addr + 4u) - 1u;
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break;
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case PMP_AMATCH_NAPOT:
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pmp_decode_napot(this_addr, &sa, &ea);
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break;
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default:
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sa = 0u;
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ea = 0u;
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break;
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}
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env->pmp_state.addr[pmp_index].sa = sa;
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env->pmp_state.addr[pmp_index].ea = ea;
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for (i = 0; i < MAX_RISCV_PMPS; i++) {
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const uint8_t a_field =
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pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
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if (PMP_AMATCH_OFF != a_field) {
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env->pmp_state.num_rules++;
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}
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}
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}
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static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
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{
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int result = 0;
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if ((addr >= env->pmp_state.addr[pmp_index].sa)
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&& (addr <= env->pmp_state.addr[pmp_index].ea)) {
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result = 1;
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} else {
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result = 0;
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}
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return result;
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}
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/*
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* Public Interface
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*/
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/*
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* Check if the address has required RWX privs to complete desired operation
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*/
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bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
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target_ulong size, pmp_priv_t privs)
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{
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int i = 0;
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int ret = -1;
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target_ulong s = 0;
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target_ulong e = 0;
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pmp_priv_t allowed_privs = 0;
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/* Short cut if no rules */
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if (0 == pmp_get_num_rules(env)) {
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return true;
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}
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/* 1.10 draft priv spec states there is an implicit order
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from low to high */
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for (i = 0; i < MAX_RISCV_PMPS; i++) {
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s = pmp_is_in_range(env, i, addr);
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e = pmp_is_in_range(env, i, addr + size);
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/* partially inside */
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if ((s + e) == 1) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"pmp violation - access is partially inside\n");
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ret = 0;
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break;
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}
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/* fully inside */
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const uint8_t a_field =
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pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
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if ((s + e) == 2) {
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if (PMP_AMATCH_OFF == a_field) {
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return 1;
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}
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allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC;
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if ((env->priv != PRV_M) || pmp_is_locked(env, i)) {
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allowed_privs &= env->pmp_state.pmp[i].cfg_reg;
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}
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if ((privs & allowed_privs) == privs) {
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ret = 1;
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break;
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} else {
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ret = 0;
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break;
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}
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}
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}
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/* No rule matched */
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if (ret == -1) {
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if (env->priv == PRV_M) {
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ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an
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* M-Mode access, the access succeeds */
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} else {
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ret = 0; /* Other modes are not allowed to succeed if they don't
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* match a rule, but there are rules. We've checked for
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* no rule earlier in this function. */
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}
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}
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return ret == 1 ? true : false;
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}
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/*
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* Handle a write to a pmpcfg CSP
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*/
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void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
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target_ulong val)
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{
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int i;
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uint8_t cfg_val;
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PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx,
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env->mhartid, reg_index, val);
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if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"ignoring pmpcfg write - incorrect address\n");
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return;
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}
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for (i = 0; i < sizeof(target_ulong); i++) {
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cfg_val = (val >> 8 * i) & 0xff;
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pmp_write_cfg(env, (reg_index * sizeof(target_ulong)) + i,
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cfg_val);
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}
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}
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/*
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* Handle a read from a pmpcfg CSP
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*/
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target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
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{
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int i;
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target_ulong cfg_val = 0;
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target_ulong val = 0;
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for (i = 0; i < sizeof(target_ulong); i++) {
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val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i);
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cfg_val |= (val << (i * 8));
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}
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PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx,
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env->mhartid, reg_index, cfg_val);
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return cfg_val;
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}
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/*
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* Handle a write to a pmpaddr CSP
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*/
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void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
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target_ulong val)
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{
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PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx,
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env->mhartid, addr_index, val);
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if (addr_index < MAX_RISCV_PMPS) {
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if (!pmp_is_locked(env, addr_index)) {
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env->pmp_state.pmp[addr_index].addr_reg = val;
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pmp_update_rule(env, addr_index);
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"ignoring pmpaddr write - locked\n");
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}
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"ignoring pmpaddr write - out of bounds\n");
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}
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}
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/*
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* Handle a read from a pmpaddr CSP
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*/
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target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
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{
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PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx,
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env->mhartid, addr_index,
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env->pmp_state.pmp[addr_index].addr_reg);
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if (addr_index < MAX_RISCV_PMPS) {
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return env->pmp_state.pmp[addr_index].addr_reg;
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"ignoring pmpaddr read - out of bounds\n");
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return 0;
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}
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}
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#endif
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