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unicorn/qemu/target/riscv
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Bastian Koppelmann e96282eb28
target/riscv: Remove decode_RV32_64G() 
decodetree handles all instructions now so the fallback is not necessary
anymore.

Backports commit 25e6ca30c668783cd72ff97080ff44e141b99f9b from qemu
2019-03-19 05:37:42 -04:00
..
insn_trans target/riscv: Rename trans_arith to gen_arith 2019-03-19 05:35:44 -04:00
cpu.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
cpu.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
cpu_bits.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
cpu_helper.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
cpu_user.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
csr.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
fpu_helper.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
helper.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
insn16.decode target/riscv: Convert quadrant 2 of RVXC insns to decodetree 2019-03-19 04:53:07 -04:00
insn32-64.decode target/riscv: Convert RV64D insns to decodetree 2019-03-18 16:57:16 -04:00
insn32.decode target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists 2019-03-19 05:17:54 -04:00
instmap.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
Makefile.objs target/riscv: Convert quadrant 0 of RVXC insns to decodetree 2019-03-19 04:45:53 -04:00
op_helper.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
pmp.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
pmp.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
translate.c target/riscv: Remove decode_RV32_64G() 2019-03-19 05:37:42 -04:00
unicorn.c target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
unicorn.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00