Richard Henderson f0bb9a7f39 target/riscv: Generate nanboxed results from trans_rvf.inc.c ... Make sure that all results from inline single-precision scalar operations are properly nan-boxed to 64-bits. Backports 40eaa473611936445ae9c63841445cfa6e36840b		2021-03-08 12:26:49 -05:00
..
trans_privileged.inc.c	target/riscv: Move the hfence instructions to the rvh decode	2021-02-25 11:59:49 -05:00
trans_rva.inc.c	tcg: TCGMemOp is now accelerator independent MemOp	2019-11-28 03:01:12 -05:00
trans_rvd.inc.c	target/riscv: fsd/fsw doesn't dirty FP state	2020-03-21 12:20:52 -04:00
trans_rvf.inc.c	target/riscv: Generate nanboxed results from trans_rvf.inc.c	2021-03-08 12:26:49 -05:00
trans_rvh.inc.c	target/riscv: Implement checks for hfence	2021-02-25 12:03:57 -05:00
trans_rvi.inc.c	tcg: TCGMemOp is now accelerator independent MemOp	2019-11-28 03:01:12 -05:00
trans_rvm.inc.c	target/riscv: Zero extend the inputs of divuw and remuw	2019-03-26 20:38:17 -04:00
trans_rvv.inc.c	target/riscv: fix vector index load/store constraints	2021-03-08 12:16:45 -05:00