Leon Alrae 272e412fc9 target-mips: flush QEMU TLB when disabling 64-bit addressing ... CP0.Status.KX/SX/UX bits are responsible for enabling access to 64-bit Kernel/Supervisor/User Segments. If bit is cleared an access to corresponding segment should generate Address Error Exception. However, the guest may still be able to access some pages belonging to the disabled 64-bit segment because we forget to flush QEMU TLB. This patch fixes it. Backports commit f93c3a8d0c0c1038dbe1e957eb8ab92671137975 from qemu		2018-02-17 19:06:43 -05:00
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cpu-qom.h
cpu.c	target-mips: implement the CPU wake-up on non-enabled interrupts in R6	2018-02-17 15:24:12 -05:00
cpu.h	target-mips: flush QEMU TLB when disabling 64-bit addressing	2018-02-17 19:06:43 -05:00
dsp_helper.c
helper.c	target-mips: Fix exceptions while UX=0	2018-02-17 18:57:52 -05:00
helper.h	target-mips: add PC, XNP reg numbers to RDHWR	2018-02-17 15:24:13 -05:00
lmi_helper.c
Makefile.objs
mips-defs.h
msa_helper.c
op_helper.c	target-mips: flush QEMU TLB when disabling 64-bit addressing	2018-02-17 19:06:43 -05:00
TODO
translate.c	target-mips: add SIGRIE instruction	2018-02-17 15:24:13 -05:00
translate_init.c	target-mips: Set Config5.XNP for R6 cores	2018-02-17 15:24:13 -05:00
unicorn.c
unicorn.h