unicorn/qemu/target
Palmer Dabbelt fc662c281a
target/riscv: Zero extend the inputs of divuw and remuw
While running the GCC test suite against 4.0.0-rc0, Kito found a
regression introduced by the decodetree conversion that caused divuw and
remuw to sign-extend their inputs. The ISA manual says they are
supposed to be zero extended:

DIVW and DIVUW instructions are only valid for RV64, and divide the
lower 32 bits of rs1 by the lower 32 bits of rs2, treating them as
signed and unsigned integers respectively, placing the 32-bit
quotient in rd, sign-extended to 64 bits. REMW and REMUW
instructions are only valid for RV64, and provide the corresponding
signed and unsigned remainder operations respectively. Both REMW
and REMUW always sign-extend the 32-bit result to 64 bits, including
on a divide by zero.

Here's Kito's reduced test case from the GCC test suite

unsigned calc_mp(unsigned mod)
{
unsigned a,b,c;
c=-1;
a=c/mod;
b=0-a*mod;
if (b > mod) { a += 1; b-=mod; }
return b;
}

int main(int argc, char *argv[])
{
unsigned x = 1234;
unsigned y = calc_mp(x);

if ((sizeof (y) == 4 && y != 680)
|| (sizeof (y) == 2 && y != 134))
abort ();
exit (0);
}

I haven't done any other testing on this, but it does fix the test case.

Backports commit f17e02cd3731bdfe2942d1d0b2a92f26da02408c from qemu
2019-03-26 20:38:17 -04:00
..
arm target/arm: make pmccntr_op_start/finish static 2019-03-26 20:35:34 -04:00
i386 i386: Disable OSPKE on CPU model definitions 2019-03-22 09:46:44 -04:00
m68k target/m68k: Correct instruction emulation 2019-02-28 19:21:49 -05:00
mips target/mips: Restore Qemu's organization of CPU definitions 2019-03-08 01:40:50 -05:00
riscv target/riscv: Zero extend the inputs of divuw and remuw 2019-03-26 20:38:17 -04:00
sparc target: Resolve repeated typedef warnings 2019-01-22 20:27:35 -05:00