Palmer Dabbelt fc662c281a target/riscv: Zero extend the inputs of divuw and remuw ... While running the GCC test suite against 4.0.0-rc0, Kito found a regression introduced by the decodetree conversion that caused divuw and remuw to sign-extend their inputs. The ISA manual says they are supposed to be zero extended: DIVW and DIVUW instructions are only valid for RV64, and divide the lower 32 bits of rs1 by the lower 32 bits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient in rd, sign-extended to 64 bits. REMW and REMUW instructions are only valid for RV64, and provide the corresponding signed and unsigned remainder operations respectively. Both REMW and REMUW always sign-extend the 32-bit result to 64 bits, including on a divide by zero. Here's Kito's reduced test case from the GCC test suite unsigned calc_mp(unsigned mod) { unsigned a,b,c; c=-1; a=c/mod; b=0-a*mod; if (b > mod) { a += 1; b-=mod; } return b; } int main(int argc, char *argv[]) { unsigned x = 1234; unsigned y = calc_mp(x); if ((sizeof (y) == 4 && y != 680) || (sizeof (y) == 2 && y != 134)) abort (); exit (0); } I haven't done any other testing on this, but it does fix the test case. Backports commit f17e02cd3731bdfe2942d1d0b2a92f26da02408c from qemu		2019-03-26 20:38:17 -04:00
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insn_trans	target/riscv: Zero extend the inputs of divuw and remuw	2019-03-26 20:38:17 -04:00
cpu.c	target/riscv: Remove unused struct	2019-03-19 23:58:31 -04:00
cpu.h	RISC-V: linux-user support for RVE ABI	2019-03-19 23:58:31 -04:00
cpu_bits.h	RISC-V: Fixes to CSR_* register macros.	2019-03-19 23:39:49 -04:00
cpu_helper.c	RISC-V: Update load reservation comment in do_interrupt	2019-03-19 23:58:31 -04:00
cpu_user.h	RISC-V: linux-user support for RVE ABI	2019-03-19 23:58:31 -04:00
csr.c	RISC-V: Add support for vectored interrupts	2019-03-19 23:58:31 -04:00
fpu_helper.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
helper.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
insn16.decode	target/riscv: Convert quadrant 2 of RVXC insns to decodetree	2019-03-19 04:53:07 -04:00
insn32-64.decode	target/riscv: Convert RV64D insns to decodetree	2019-03-18 16:57:16 -04:00
insn32.decode	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	2019-03-19 05:17:54 -04:00
instmap.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
Makefile.objs	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	2019-03-19 04:45:53 -04:00
op_helper.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
pmp.c	riscv: pmp: Log pmp access errors as guest errors	2019-03-19 23:45:03 -04:00
pmp.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
translate.c	target/riscv: Zero extend the inputs of divuw and remuw	2019-03-26 20:38:17 -04:00
unicorn.c	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
unicorn.h	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00