begone test

.gitignore

@@ -1,3 +1,3 @@
 /target
-
-test/
+test
+output

Cargo.toml

@@ -7,6 +7,10 @@ edition = "2021"
 
 [dependencies]
 
+[[bin]]
+name = "emulator"
+path = "src/emulator/main.rs"
+
 [[bin]]
 name = "disassembler"
 path = "src/disassembler/main.rs"

src/disassembler/main.rs

@@ -1,9 +1,9 @@
 #![allow(clippy::useless_format)]
 #![allow(clippy::too_many_lines)]
-use core::slice::Iter;
 use std::{env, fs};
 
 const REGISTERS: [&str; 8] = ["B", "C", "D", "E", "H", "L", "M", "A"];
+const PRINT_MEMLOC: bool = true;
 
 fn main() {
     let mut args = env::args();
@@ -12,80 +12,85 @@ fn main() {
         .expect("Provide a path to a file to disassemble as an argument");
     let file = fs::read(filename).expect("where file");
     let mut data = file.iter();
+    let mut index: u32 = 0;
 
     while let Some(byte) = data.next() {
-        fn next(data: &mut Iter<u8>, len: u8) -> String {
+        let current_index = index.clone();
+        index += 1;
+
+        let mut next = |len: u8| {
             let mut res = String::new();
+            index += len as u32;
 
             for _ in 0..len {
                 res.insert_str(
                     0,
-                    format!("{:x}", data.next().expect("Expected data")).as_str(),
+                    format!("{:02x}", data.next().expect("Expected data")).as_str(),
                 );
             }
 
             res
-        }
+        };
 
         // http://www.emulator101.com/reference/8080-by-opcode.html
 
         let instruction: String = match byte {
             0x00 => format!("NOP"),
-            0x01 => format!("LXI    B,#${}", next(&mut data, 2)),
+            0x01 => format!("LXI    B,#${}", next(2)),
             0x02 => format!("STAX   B"),
             0x03 => format!("INX    B"),
             0x04 => format!("INR    B"),
             0x05 => format!("DCR    B"),
-            0x06 => format!("MVI    B,#0x{}", next(&mut data, 1)),
+            0x06 => format!("MVI    B,#${}", next(1)),
             0x07 => format!("RLC"),
             0x09 => format!("DAD    B"),
             0x0a => format!("LDAX   B"),
             0x0b => format!("DCX    B"),
             0x0c => format!("INR    C"),
             0x0d => format!("DCR    C"),
-            0x0e => format!("MVI    C,#0x{}", next(&mut data, 1)),
+            0x0e => format!("MVI    C,#${}", next(1)),
             0x0f => format!("RRC"),
-            0x11 => format!("LXI    D,#0x{}", next(&mut data, 2)),
+            0x11 => format!("LXI    D,#${}", next(2)),
             0x12 => format!("STAX   D"),
             0x13 => format!("INX    D"),
             0x14 => format!("INR    D"),
             0x15 => format!("DCR    D"),
-            0x16 => format!("MVI    D,#0x{}", next(&mut data, 1)),
+            0x16 => format!("MVI    D,#${}", next(1)),
             0x17 => format!("RAL"),
             0x19 => format!("DAD    D"),
             0x1a => format!("LDAX   D"),
             0x1b => format!("DCX    D"),
             0x1c => format!("INR    E"),
             0x1d => format!("DCR    E"),
-            0x1e => format!("MVI    E,#0x{}", next(&mut data, 1)),
+            0x1e => format!("MVI    E,#${}", next(1)),
             0x1f => format!("RAR"),
-            0x21 => format!("LXI    H,#0x{}", next(&mut data, 2)),
-            0x22 => format!("SLHD   #0x{}", next(&mut data, 2)),
+            0x21 => format!("LXI    H,#${}", next(2)),
+            0x22 => format!("SLHD   #${}", next(2)),
             0x23 => format!("INX    H"),
             0x24 => format!("INR    H"),
             0x25 => format!("DCR    H"),
-            0x26 => format!("MVI    H,#0x{}", next(&mut data, 1)),
+            0x26 => format!("MVI    H,#${}", next(1)),
             0x27 => format!("DAA"),
             0x29 => format!("DAD    H"),
-            0x2a => format!("LHLD   ${}", next(&mut data, 2)),
+            0x2a => format!("LHLD   ${}", next(2)),
             0x2b => format!("DCX    H"),
             0x2c => format!("INR    L"),
             0x2d => format!("DCR    L"),
-            0x2e => format!("MVI    L,#0x{}", next(&mut data, 1)),
+            0x2e => format!("MVI    L,#${}", next(1)),
             0x2f => format!("CMA"),
-            0x31 => format!("LXI    SP,#0x{}", next(&mut data, 2)),
-            0x32 => format!("STA    ${}", next(&mut data, 2)),
+            0x31 => format!("LXI    SP,#${}", next(2)),
+            0x32 => format!("STA    ${}", next(2)),
             0x33 => format!("INX    SP"),
             0x34 => format!("INR    M"),
             0x35 => format!("DCR    M"),
-            0x36 => format!("MVI    M,#0x{}", next(&mut data, 1)),
+            0x36 => format!("MVI    M,#${}", next(1)),
             0x37 => format!("STC"),
             0x39 => format!("DAD    SP"),
-            0x3a => format!("LDA    ${}", next(&mut data, 2)),
+            0x3a => format!("LDA    ${}", next(2)),
             0x3b => format!("DCX    SP"),
             0x3c => format!("INR    A"),
             0x3d => format!("DCR    A"),
-            0x3e => format!("MVI    A,#0x{}", next(&mut data, 1)),
+            0x3e => format!("MVI    A,#${}", next(1)),
             0x3f => format!("CMC"),
             0x76 => format!("HLT             ; Trigger interrupt"),
             0x40..=0x7f // Test this!
@@ -108,66 +113,71 @@ fn main() {
                  => format!("CMP    {}", REGISTERS[(byte & 0b111) as usize]),
             0xc0 => format!("RNZ"),
             0xc1 => format!("POP    B"),
-            0xc2 => format!("JNZ    ${}", next(&mut data, 2)),
-            0xc3 => format!("JMP    ${}", next(&mut data, 2)),
-            0xc4 => format!("CNZ    ${}", next(&mut data, 2)),
+            0xc2 => format!("JNZ    ${}", next(2)),
+            0xc3 => format!("JMP    ${}", next(2)),
+            0xc4 => format!("CNZ    ${}", next(2)),
             0xc5 => format!("PUSH   B"),
-            0xc6 => format!("ADI    #0x{}", next(&mut data, 1)),
+            0xc6 => format!("ADI    #${}", next(1)),
             0xc7 => format!("RST    0        ; CALL $0"),
             0xc8 => format!("RZ"),
             0xc9 => format!("RET"),
-            0xca => format!("JZ     ${}", next(&mut data, 2)),
-            0xcc => format!("CZ     ${}", next(&mut data, 2)),
-            0xcd => format!("CALL   ${}", next(&mut data, 2)),
-            0xce => format!("ACI    #0x{}", next(&mut data, 1)),
+            0xca => format!("JZ     ${}", next(2)),
+            0xcc => format!("CZ     ${}", next(2)),
+            0xcd => format!("CALL   ${}", next(2)),
+            0xce => format!("ACI    #${}", next(1)),
             0xcf => format!("RST    1        ; CALL $8"),
             0xd0 => format!("RNC"),
             0xd1 => format!("POP    D"),
-            0xd2 => format!("JNC    ${}", next(&mut data, 2)),
-            0xd3 => format!("OUT    #0x{}", next(&mut data, 1)),
-            0xd4 => format!("CNC    ${}", next(&mut data, 2)),
+            0xd2 => format!("JNC    ${}", next(2)),
+            0xd3 => format!("OUT    #${}", next(1)),
+            0xd4 => format!("CNC    ${}", next(2)),
             0xd5 => format!("PUSH   D"),
-            0xd6 => format!("SUI    #0x{}", next(&mut data, 1)),
+            0xd6 => format!("SUI    #${}", next(1)),
             0xd7 => format!("RST    2        ; CALL $10"),
             0xd8 => format!("RC"),
-            0xda => format!("JC     ${}", next(&mut data, 2)),
-            0xdb => format!("IN     #0x{}", next(&mut data, 1)),
-            0xdc => format!("CC     ${}", next(&mut data, 2)),
-            0xde => format!("SBI    #0x{}", next(&mut data, 1)),
+            0xda => format!("JC     ${}", next(2)),
+            0xdb => format!("IN     #${}", next(1)),
+            0xdc => format!("CC     ${}", next(2)),
+            0xde => format!("SBI    #${}", next(1)),
             0xdf => format!("RST    3        ; $CALL 18"),
             0xe0 => format!("RPO"),
             0xe1 => format!("POP    H"),
-            0xe2 => format!("JPO    ${}", next(&mut data, 2)),
+            0xe2 => format!("JPO    ${}", next(2)),
             0xe3 => format!("XTHL"),
-            0xe4 => format!("CPO    ${}", next(&mut data, 2)),
+            0xe4 => format!("CPO    ${}", next(2)),
             0xe5 => format!("PUSH   H"),
-            0xe6 => format!("ANI    #0x{}", next(&mut data, 1)),
+            0xe6 => format!("ANI    #${}", next(1)),
             0xe7 => format!("RST    4        ; CALL $20"),
             0xe8 => format!("RPE"),
             0xe9 => format!("PCHL"),
-            0xea => format!("JPE    ${}", next(&mut data, 2)),
+            0xea => format!("JPE    ${}", next(2)),
             0xeb => format!("XCHG"),
-            0xec => format!("CPE    ${}", next(&mut data, 2)),
-            0xee => format!("XRI    #0x{}", next(&mut data, 1)),
+            0xec => format!("CPE    ${}", next(2)),
+            0xee => format!("XRI    #${}", next(1)),
             0xef => format!("RST    5        ; CALL $28"),
             0xf0 => format!("RP"),
             0xf1 => format!("POP    PSW"),
-            0xf2 => format!("JP     ${}", next(&mut data, 2)),
+            0xf2 => format!("JP     ${}", next(2)),
             0xf3 => format!("DI"),
-            0xf4 => format!("CP     ${}", next(&mut data, 2)),
+            0xf4 => format!("CP     ${}", next(2)),
             0xf5 => format!("PUSH   PSW"),
-            0xf6 => format!("ORI    #0x{}", next(&mut data, 1)),
+            0xf6 => format!("ORI    #${}", next(1)),
             0xf7 => format!("RST    6        ; CALL $30"),
             0xf8 => format!("RM"),
             0xf9 => format!("SPHL"),
-            0xfa => format!("JM     ${}", next(&mut data, 2)),
+            0xfa => format!("JM     ${}", next(2)),
             0xfb => format!("EI"),
-            0xfc => format!("CM     ${}", next(&mut data, 2)),
-            0xfe => format!("CPI    #0x{}", next(&mut data, 1)),
+            0xfc => format!("CM     ${}", next(2)),
+            0xfe => format!("CPI    #${}", next(1)),
             0xff => format!("RST    7        ; CALL $38"),
-            _ => panic!("Unimplemented instruction {byte:#x}"),
+            _    => format!("; Unknown instruction {byte:#x}"),
+            // _ => panic!("Unimplemented instruction {byte:#x}"),
         };
 
-        println!("{instruction}");
+        if PRINT_MEMLOC {
+            println!("{:04x} {}", current_index, instruction);
+        } else {
+            println!("{instruction}");
+        }
     }
 }

src/emulator/instructions/arithmetic.rs

@@ -0,0 +1,69 @@
+use crate::{EmulatorState, Register, get_register, structs::set_register};
+
+/// Sets the condition code flags according to `result`. `flags` parameter
+/// indicates which flags will be set, 0b1111 will set all (Z, S, C, P)
+/// while 0b1000 will only set Z.
+fn set_cc(state: &mut EmulatorState, result: u16, flags: u8) {
+    if flags & 0b1000 > 0 { state.cc.z = (result & 0xff) == 0; }
+    if flags & 0b0100 > 0 { state.cc.s = (result & 0x80) > 0; }
+    if flags & 0b0010 > 0 { state.cc.c = result > 0xff; }
+    if flags & 0b0001 > 0 { state.cc.p = (result & 0xff).count_ones() % 2 == 0; }
+}
+
+/// Add values of `register` and `A`
+pub fn add(register: Register, state: &mut EmulatorState) {
+    let result = get_register(&register, state) as u16 + state.a as u16;
+    set_cc(state, result, 0b1111);
+    state.a = (result & 0xff) as u8;
+}
+
+/// Add values of input byte and `A`
+pub fn adi(byte: u8, state: &mut EmulatorState) {
+    let result = state.a as u16 + byte as u16;
+    set_cc(state, result, 0b1111);
+    state.a = result as u8;
+}
+
+/// Add values of `register` and `A` and add +1 if carry bit is set
+pub fn adc(register: Register, state: &mut EmulatorState) {
+    let result = get_register(&register, state) as u16 + state.a as u16 + if state.cc.c { 1 } else { 0 };
+    set_cc(state, result, 0b1111);
+    state.a = (result & 0xff) as u8;
+}
+
+/// Add values of input byte and `A` and add +1 if carry bit is set
+pub fn aci(byte: u8, state: &mut EmulatorState) {
+    let result = state.a as u16 + byte as u16 + if state.cc.c { 1 } else { 0 };
+    set_cc(state, result, 0b1111);
+    state.a = result as u8;
+}
+
+/// Double precision add - Add B&C, D&E or H&L to H&L
+pub fn dad(register: Register, state: &mut EmulatorState) {
+    let num = match register {
+        Register::B  => u16::from_le_bytes([state.c, state.b]),
+        Register::D  => u16::from_le_bytes([state.e, state.d]),
+        Register::H  => u16::from_le_bytes([state.l, state.h]),
+        Register::SP => state.sp,
+        _ => panic!("Cannot perform DAD on register {:?}", register),
+    };
+
+    let (result, overflow) = num.overflowing_add(u16::from_le_bytes([state.l, state.h]));
+    state.cc.c = overflow;
+    state.h = (result >> 8) as u8;
+    state.l = result as u8;
+}
+
+/// Increase register
+pub fn inr(register: Register, state: &mut EmulatorState) {
+    let (result, _) = get_register(&register, state).overflowing_add(1);
+    set_cc(state, result as u16, 0b1101);
+    set_register(&register, result, state);
+}
+
+/// Decrease register
+pub fn dcr(register: Register, state: &mut EmulatorState) {
+    let (result, _) = get_register(&register, state).overflowing_sub(1);
+    set_cc(state, result as u16, 0b1101);
+    set_register(&register, result, state);
+}

src/emulator/instructions/mod.rs

@@ -0,0 +1 @@
+pub mod arithmetic;

src/emulator/main.rs

@@ -0,0 +1,109 @@
+use std::{fs, env};
+use instructions::arithmetic;
+
+use crate::structs::*;
+
+mod instructions;
+mod structs;
+
+pub const MEMORY_SIZE: usize = 8192;
+
+fn main() {
+    let mut state = EmulatorState {
+        a: 0,
+        b: 0,
+        c: 0,
+        d: 0,
+        e: 0,
+        h: 0,
+        l: 0,
+        sp: 0,
+        cc: ConditionCodes { z: true, s: true, p: true, c: true },
+        pc: 0,
+        ei: true,
+        memory: [0; MEMORY_SIZE],
+    };
+
+    // Load the ROM into memory
+    let mut args = env::args();
+    let filename = args
+        .nth(1)
+        .expect("Provide a path to a ROM file to emulate as an argument");
+    let file = fs::read(filename).expect("where file");
+
+    for i in 0..(MEMORY_SIZE.min(file.len())) {
+        state.memory[i] = file[i];
+    }
+
+    while state.pc < MEMORY_SIZE as u16 {
+        tick(&mut state);
+    }
+
+    println!("Program counter reached end of memory; exiting");
+    print_state(&state);
+}
+
+fn tick(state: &mut EmulatorState) {
+    let instruction = state.memory[state.pc as usize];
+
+    let mut next_byte = || {
+        state.pc += 1;
+        return state.memory[state.pc as usize];
+    };
+
+    match instruction {
+        0x00 => {} // NOP
+
+        /* Maths */
+
+        // INR
+        0x04 => arithmetic::inr(Register::B, state),
+        0x0c => arithmetic::inr(Register::C, state),
+        0x14 => arithmetic::inr(Register::D, state),
+        0x1c => arithmetic::inr(Register::E, state),
+        0x24 => arithmetic::inr(Register::H, state),
+        0x2c => arithmetic::inr(Register::L, state),
+        0x34 => arithmetic::inr(Register::M, state),
+        0x3c => arithmetic::inr(Register::A, state),
+
+        // DCR
+        0x05 => arithmetic::dcr(Register::B, state),
+        0x0d => arithmetic::dcr(Register::C, state),
+        0x15 => arithmetic::dcr(Register::D, state),
+        0x1d => arithmetic::dcr(Register::E, state),
+        0x25 => arithmetic::dcr(Register::H, state),
+        0x2d => arithmetic::dcr(Register::L, state),
+        0x35 => arithmetic::dcr(Register::M, state),
+        0x3d => arithmetic::dcr(Register::A, state),
+
+        // DAD
+        0x09 => arithmetic::dad(Register::B, state),
+        0x19 => arithmetic::dad(Register::D, state),
+        0x29 => arithmetic::dad(Register::H, state),
+        0x39 => arithmetic::dad(Register::SP, state),
+
+        0x80..=0x87 => arithmetic::add(register_from_num(instruction & 0xf), state), // ADD
+        0x88..=0x8f => arithmetic::adc(register_from_num(instruction & 0xf), state), // ADC
+        0xc6        => arithmetic::adi(next_byte(), state), // ADI
+        0xce        => arithmetic::aci(next_byte(), state), // ACI
+
+
+        /* Special */
+        0xfb => state.ei = true,  // EI
+        0xf3 => state.ei = false, // DI
+        0x76 => if state.ei { todo!() } else {     // HLT
+            println!("HLT called after DI; exiting.");
+            print_state(state);
+            std::process::exit(0);
+        },
+
+        _ => not_implemented(state),
+    }
+
+    state.pc += 1;
+}
+
+fn not_implemented(state: &EmulatorState) {
+    let instruction = state.memory[state.pc as usize];
+    panic!("Unimplemented instruction {:#02X} at {:#04X}", instruction, state.pc);
+}

src/emulator/structs.rs

@@ -0,0 +1,103 @@
+use crate::MEMORY_SIZE;
+
+pub struct EmulatorState {
+    pub a: u8,
+    pub b: u8,
+    pub c: u8,
+    pub d: u8,
+    pub e: u8,
+    pub h: u8,
+    pub l: u8,
+
+    pub cc: ConditionCodes,
+
+    /// Stack pointer
+    pub sp: u16,
+    /// Memory pointer
+    pub pc: u16,
+    /// Enable interrupts
+    pub ei: bool,
+    /// Memory map
+    pub memory: [u8; MEMORY_SIZE],
+}
+
+pub struct ConditionCodes {
+    /// Zero (Z), set if the result is zero.
+    pub z: bool,
+    /// Sign (S), set if the result is negative.
+    pub s: bool,
+    /// Parity (P), set if the number of 1 bits in the result is even.
+    pub p: bool,
+    /// Carry (C), set if the last addition operation resulted in a carry or if the last subtraction operation required a borrow.
+    pub c: bool,
+    // Auxiliary carry (AC or H), used for binary-coded decimal arithmetic (BCD).
+    // Can't test this so I won't implement it
+    // ac: bool,
+}
+
+#[derive(PartialEq)]
+#[derive(Debug)]
+pub enum Register {
+    B, C, D, E,
+    H, L, M, A,
+    SP,
+}
+
+/// Returns a Register enum based on the input number 0..7 in the order B,C,D,E,H,L,M,A
+pub fn register_from_num(b: u8) -> Register {
+    match b {
+        0 => Register::B,
+        1 => Register::C,
+        2 => Register::D,
+        3 => Register::E,
+        4 => Register::H,
+        5 => Register::L,
+        6 => Register::M,
+        7 => Register::A,
+        _ => panic!("'{b}' cannot be converted to register enum"),
+    }
+}
+
+pub fn get_register(register: &Register, state: &EmulatorState) -> u8 {
+    match register {
+        Register::B => state.b as u8,
+        Register::C => state.c as u8,
+        Register::D => state.d as u8,
+        Register::E => state.e as u8,
+        Register::H => state.h as u8,
+        Register::L => state.l as u8,
+        Register::A => state.a as u8,
+        Register::M => state.memory[u16::from_le_bytes([state.l, state.h]) as usize],
+        Register::SP => unreachable!(),
+    }
+}
+
+pub fn set_register(register: &Register, value: u8, state: &mut EmulatorState) {
+    match register {
+        Register::B => state.b = value,
+        Register::C => state.c = value,
+        Register::D => state.d = value,
+        Register::E => state.e = value,
+        Register::H => state.h = value,
+        Register::L => state.l = value,
+        Register::A => state.a = value,
+        Register::M => state.memory[u16::from_le_bytes([state.l, state.h]) as usize] = value,
+        Register::SP => panic!("Cannot set 'SP' through set_register()"),
+    };
+}
+
+/// Print values of registers and flags to stdout
+pub fn print_state(state: &EmulatorState) {
+    // State
+    println!("\nsp\tpc\tei");
+    println!("{:#06x}\t{:#06x}\t{}", state.sp, state.pc, state.ei);
+
+    // Registers
+    println!("\nB\tC\tD\tE\tH\tL\tA");
+    println!("{:#04x}\t{:#04x}\t{:#04x}\t{:#04x}\t{:#04x}\t{:#04x}\t{:#04x}",
+             state.b, state.c, state.d, state.e, state.h, state.l, state.a);
+
+    // Flags
+    println!("\nz\ts\tp\tc");
+    println!("{}\t{}\t{}\t{}", state.cc.z, state.cc.s, state.cc.p, state.cc.c);
+}