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Fix support for TU102 and TU106.

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Jonathan Johansson 2021-02-27 17:15:17 +01:00
parent cf01e2fbbd
commit 0675b563ac
2 changed files with 94 additions and 64 deletions
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15
vgpu_unlock
View file

@ -40,8 +40,10 @@ script_source = r"""
// These are the observed values for the op_type member. // These are the observed values for the op_type member.
var OP_READ_DEV_TYPE = 0x800289; // *result type is uint64_t. var OP_READ_DEV_TYPE = 0x800289; // *result type is uint64_t.
var OP_READ_PCI_ID = 0x20801801; // *result type in uint32_t, the uppper 16 var OP_READ_PCI_ID = 0x20801801; // *result type is uint16_t[4], the second
// bits is the device ID. // element (index 1) is the device ID, the
// forth element (index 3) is the subsystem
// ID.
// nvidia-vgpu-mgr expects this value for a vGPU capable GPU. // nvidia-vgpu-mgr expects this value for a vGPU capable GPU.
var DEV_TYPE_VGPU_CAPABLE = uint64(3); var DEV_TYPE_VGPU_CAPABLE = uint64(3);
@ -55,7 +57,6 @@ script_source = r"""
Interceptor.attach(Module.getExportByName(null, "ioctl"), { Interceptor.attach(Module.getExportByName(null, "ioctl"), {
onEnter(args) { onEnter(args) {
console.log("ioctl called");
this.request = args[1]; this.request = args[1];
this.argp = args[2]; this.argp = args[2];
}, },
@ -81,15 +82,17 @@ script_source = r"""
var op_type = this.argp.add(8).readU32(); var op_type = this.argp.add(8).readU32();
if(op_type == OP_READ_PCI_ID) { if(op_type == OP_READ_PCI_ID) {
// Lookup address of the device ID, note that we point directly at // Lookup address of the device and subsystem IDs.
// the upper 16 bits of the word.
var devid_ptr = this.argp.add(0x10).readPointer().add(2); var devid_ptr = this.argp.add(0x10).readPointer().add(2);
var subsysid_ptr = this.argp.add(0x10).readPointer().add(6);
// Now we replace the device ID with a spoofed value that needs to // Now we replace the device ID with a spoofed value that needs to
// be determined such that the spoofed value represents a GPU with // be determined such that the spoofed value represents a GPU with
// vGPU support that uses the same GPU chip as our actual GPU. // vGPU support that uses the same GPU chip as our actual GPU.
var actual_devid = devid_ptr.readU16(); var actual_devid = devid_ptr.readU16();
var spoofed_devid = actual_devid; var spoofed_devid = actual_devid;
var actual_subsysid = subsysid_ptr.readU16();
var spoofed_subsysid = actual_subsysid;
// GP102 // GP102
if(actual_devid == 0x1b00 || // TITAN X (Pascal) if(actual_devid == 0x1b00 || // TITAN X (Pascal)
@ -114,6 +117,7 @@ script_source = r"""
actual_devid == 0x1e04 || // RTX 2080 Ti actual_devid == 0x1e04 || // RTX 2080 Ti
actual_devid == 0x1e07) { // RTX 2080 Ti Rev. A actual_devid == 0x1e07) { // RTX 2080 Ti Rev. A
spoofed_devid = 0x1e30; // Quadro RTX 6000 spoofed_devid = 0x1e30; // Quadro RTX 6000
spoofed_subsysid = 0x12ba;
} }
// TU104 // TU104
@ -135,6 +139,7 @@ script_source = r"""
} }
devid_ptr.writeU16(spoofed_devid); devid_ptr.writeU16(spoofed_devid);
subsysid_ptr.writeU16(spoofed_subsysid);
} }
if(op_type == OP_READ_DEV_TYPE) { if(op_type == OP_READ_DEV_TYPE) {

65
vgpu_unlock_hooks.c
View file

@ -561,7 +561,7 @@ static void vgpu_unlock_hmac_sha256(void* dst,
*/ */
/* Debug logs can be enabled here. */ /* Debug logs can be enabled here. */
#if 1 #if 0
#define LOG(...) printk(__VA_ARGS__) #define LOG(...) printk(__VA_ARGS__)
#else #else
#define LOG(...) #define LOG(...)
@ -580,7 +580,7 @@ typedef struct {
uint16_t subsys_id; uint16_t subsys_id;
uint16_t subsys_vend_id; /* Check skipped if zero. */ uint16_t subsys_vend_id; /* Check skipped if zero. */
uint8_t unk1[7]; uint8_t unk1[7];
char name[15]; char name[31];
uint8_t sign[0x20]; uint8_t sign[0x20];
} }
__attribute__((packed)) __attribute__((packed))
@ -631,24 +631,49 @@ static vgpu_unlock_vgpu_t vgpu_unlock_vgpu[] =
{ 2, 0x1007, 0x1bb3, 0, 0x1380, 0, { 0 }, { "GRID P4-8C" } }, { 2, 0x1007, 0x1bb3, 0, 0x1380, 0, { 0 }, { "GRID P4-8C" } },
{ 2, 0x1007, 0x1bb3, 0, 0x1385, 0, { 0 }, { "GRID P4-4C" } }, { 2, 0x1007, 0x1bb3, 0, 0x1385, 0, { 0 }, { "GRID P4-4C" } },
/* Quadro RTX 6000 */
{ 3, 0x1007, 0x1e30, 0, 0x1325, 0, { 0 }, { "GRID RTX6000-1Q" } },
{ 3, 0x1007, 0x1e30, 0, 0x1326, 0, { 0 }, { "GRID RTX6000-2Q" } },
{ 3, 0x1007, 0x1e30, 0, 0x1327, 0, { 0 }, { "GRID RTX6000-3Q" } },
{ 3, 0x1007, 0x1e30, 0, 0x1328, 0, { 0 }, { "GRID RTX6000-4Q" } },
{ 3, 0x1007, 0x1e30, 0, 0x1329, 0, { 0 }, { "GRID RTX6000-6Q" } },
{ 3, 0x1007, 0x1e30, 0, 0x132a, 0, { 0 }, { "GRID RTX6000-8Q" } },
{ 3, 0x1007, 0x1e30, 0, 0x132b, 0, { 0 }, { "GRID RTX6000-12Q" } },
{ 3, 0x1007, 0x1e30, 0, 0x132c, 0, { 0 }, { "GRID RTX6000-24Q" } },
{ 3, 0x1007, 0x1e30, 0, 0x13bf, 0, { 0 }, { "GRID RTX6000-4C" } },
{ 3, 0x1007, 0x1e30, 0, 0x13c0, 0, { 0 }, { "GRID RTX6000-6C" } },
{ 3, 0x1007, 0x1e30, 0, 0x13c1, 0, { 0 }, { "GRID RTX6000-8C" } },
{ 3, 0x1007, 0x1e30, 0, 0x13c2, 0, { 0 }, { "GRID RTX6000-12C" } },
{ 3, 0x1007, 0x1e30, 0, 0x13c3, 0, { 0 }, { "GRID RTX6000-24C" } },
{ 3, 0x1007, 0x1e30, 0, 0x1437, 0, { 0 }, { "GRID RTX6000-1B" } },
{ 3, 0x1007, 0x1e30, 0, 0x1438, 0, { 0 }, { "GRID RTX6000-2B" } },
{ 3, 0x1007, 0x1e30, 0, 0x1439, 0, { 0 }, { "GRID RTX6000-1A" } },
{ 3, 0x1007, 0x1e30, 0, 0x143a, 0, { 0 }, { "GRID RTX6000-2A" } },
{ 3, 0x1007, 0x1e30, 0, 0x143b, 0, { 0 }, { "GRID RTX6000-3A" } },
{ 3, 0x1007, 0x1e30, 0, 0x143c, 0, { 0 }, { "GRID RTX6000-4A" } },
{ 3, 0x1007, 0x1e30, 0, 0x143d, 0, { 0 }, { "GRID RTX6000-6A" } },
{ 3, 0x1007, 0x1e30, 0, 0x143e, 0, { 0 }, { "GRID RTX6000-8A" } },
{ 3, 0x1007, 0x1e30, 0, 0x143f, 0, { 0 }, { "GRID RTX6000-12A" } },
{ 3, 0x1007, 0x1e30, 0, 0x1440, 0, { 0 }, { "GRID RTX6000-24A" } },
/* Tesla T4 */ /* Tesla T4 */
{ 2, 0x1007, 0x1e30, 0, 0x1309, 0, { 0 }, { "GRID T4-1B" } }, { 2, 0x1007, 0x1eb8, 0, 0x1309, 0, { 0 }, { "GRID T4-1B" } },
{ 2, 0x1007, 0x1e30, 0, 0x130a, 0, { 0 }, { "GRID T4-2B" } }, { 2, 0x1007, 0x1eb8, 0, 0x130a, 0, { 0 }, { "GRID T4-2B" } },
{ 2, 0x1007, 0x1e30, 0, 0x130b, 0, { 0 }, { "GRID T4-2B4" } }, { 2, 0x1007, 0x1eb8, 0, 0x130b, 0, { 0 }, { "GRID T4-2B4" } },
{ 2, 0x1007, 0x1e30, 0, 0x130c, 0, { 0 }, { "GRID T4-1Q" } }, { 2, 0x1007, 0x1eb8, 0, 0x130c, 0, { 0 }, { "GRID T4-1Q" } },
{ 2, 0x1007, 0x1e30, 0, 0x130d, 0, { 0 }, { "GRID T4-2Q" } }, { 2, 0x1007, 0x1eb8, 0, 0x130d, 0, { 0 }, { "GRID T4-2Q" } },
{ 2, 0x1007, 0x1e30, 0, 0x130e, 0, { 0 }, { "GRID T4-4Q" } }, { 2, 0x1007, 0x1eb8, 0, 0x130e, 0, { 0 }, { "GRID T4-4Q" } },
{ 2, 0x1007, 0x1e30, 0, 0x130f, 0, { 0 }, { "GRID T4-8Q" } }, { 2, 0x1007, 0x1eb8, 0, 0x130f, 0, { 0 }, { "GRID T4-8Q" } },
{ 2, 0x1007, 0x1e30, 0, 0x1310, 0, { 0 }, { "GRID T4-16Q" } }, { 2, 0x1007, 0x1eb8, 0, 0x1310, 0, { 0 }, { "GRID T4-16Q" } },
{ 2, 0x1007, 0x1e30, 0, 0x1311, 0, { 0 }, { "GRID T4-1A" } }, { 2, 0x1007, 0x1eb8, 0, 0x1311, 0, { 0 }, { "GRID T4-1A" } },
{ 2, 0x1007, 0x1e30, 0, 0x1312, 0, { 0 }, { "GRID T4-2A" } }, { 2, 0x1007, 0x1eb8, 0, 0x1312, 0, { 0 }, { "GRID T4-2A" } },
{ 2, 0x1007, 0x1e30, 0, 0x1313, 0, { 0 }, { "GRID T4-4A" } }, { 2, 0x1007, 0x1eb8, 0, 0x1313, 0, { 0 }, { "GRID T4-4A" } },
{ 2, 0x1007, 0x1e30, 0, 0x1314, 0, { 0 }, { "GRID T4-8A" } }, { 2, 0x1007, 0x1eb8, 0, 0x1314, 0, { 0 }, { "GRID T4-8A" } },
{ 2, 0x1007, 0x1e30, 0, 0x1315, 0, { 0 }, { "GRID T4-16A" } }, { 2, 0x1007, 0x1eb8, 0, 0x1315, 0, { 0 }, { "GRID T4-16A" } },
{ 2, 0x1007, 0x1e30, 0, 0x1345, 0, { 0 }, { "GRID T4-1B4" } }, { 2, 0x1007, 0x1eb8, 0, 0x1345, 0, { 0 }, { "GRID T4-1B4" } },
{ 2, 0x1007, 0x1e30, 0, 0x1375, 0, { 0 }, { "GRID T4-16C" } }, { 2, 0x1007, 0x1eb8, 0, 0x1375, 0, { 0 }, { "GRID T4-16C" } },
{ 2, 0x1007, 0x1e30, 0, 0x139a, 0, { 0 }, { "GRID T4-4C" } }, { 2, 0x1007, 0x1eb8, 0, 0x139a, 0, { 0 }, { "GRID T4-4C" } },
{ 2, 0x1007, 0x1e30, 0, 0x139b, 0, { 0 }, { "GRID T4-8C" } }, { 2, 0x1007, 0x1eb8, 0, 0x139b, 0, { 0 }, { "GRID T4-8C" } },
{ 0 } /* Sentinel */ { 0 } /* Sentinel */
}; };
@ -710,7 +735,7 @@ static uint16_t vgpu_unlock_pci_devid_to_vgpu_capable(uint16_t pci_devid)
case 0x1e89: /* RTX 2060 */ case 0x1e89: /* RTX 2060 */
case 0x1eb0: /* Quadro RTX 5000 */ case 0x1eb0: /* Quadro RTX 5000 */
case 0x1eb1: /* Quadro RTX 4000 */ case 0x1eb1: /* Quadro RTX 4000 */
return 0x1eb8; /* Tesla P4 */ return 0x1eb8; /* Tesla T4 */
/* GA102 */ /* GA102 */
case 0x2204: /* RTX 3090 */ case 0x2204: /* RTX 3090 */