ryujinx/ChocolArm64
1
0
Fork 0
mirror of https://github.com/Ryujinx/ChocolArm64.git synced 2024-12-22 14:25:34 +00:00
Code Issues Packages Projects Releases Wiki Activity
190 commits 1 branch 0 tags 888 KiB
Commit graph

190 commits

This branch
This branch
All branches
Author SHA1 Message Date
gdkchan ed80772500 Add the FADDP (scalar) instruction 2018-06-18 00:41:28 -03:00
riperiperi 05ef572474 Faster soft implementation of smulh and umulh (#134) 
* Faster soft implementation of smulh and umulh

* smulh: Fixed mul with 0 acting like it had a negative result.

* Use compliment for negative smulh result.
 2018-06-13 10:55:45 -03:00
Lordmau5 d99c39b448 Implement Fabs_V (#146) 2018-06-12 09:29:16 -03:00
gdkchan 231539a9e8 Move WriteBytes to AMemory, implement it with a Marshal copy like ReadBytes, fix regression on address range checking 2018-06-09 13:05:41 -03:00
gdkchan 0e8fd39636 Small cleanup in AMemory and removed some unused usings 2018-06-08 23:54:50 -03:00
gdkchan 1743dde334 Do not inline the scalar vector load methods as a workaround to a .net JIT bug 2018-06-08 23:49:53 -03:00
gdkchan eafe47fee0 Texture/Vertex/Index data cache (#132) 
* Initial implementation of the texture cache

* Cache vertex and index data aswell, some cleanup

* Improve handling of the cache by storing cached ranges on a list for each page

* Delete old data from the caches automatically, ensure that the cache is cleaned when the mapping/size changes, and some general cleanup
 2018-06-08 21:15:56 -03:00
riperiperi 81b59077f8 ReadBytes function in AMemory, with cleaner range check. (#136) 2018-06-08 21:15:02 -03:00
gdkchan f1027d5511 Force inline some of the vector read/write methods 2018-06-04 16:11:11 -03:00
gdkchan 65f781ae7b Fix mistake on astc conversion, make some static methods that shouldn't be public private, remove old commmented out code 2018-06-02 11:44:52 -03:00
gdkchan 7869b7e257 Added support for more shader instructions and texture formats, fix swapped channels in RGB565 and RGBA5551? texture formats, allow zero values on blending registers, initial work to build CFG on the shader decoder, update the BRA instruction to work with it (WIP) 2018-05-29 20:37:10 -03:00
gdkchan 09b194aaf0 Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now) 2018-05-26 17:50:47 -03:00
gdkchan d29632d7de Fix wrong type on CMTST instruction 2018-05-23 12:57:28 -03:00
gdkchan e54a0ff9c6 Remove some calls generated on the CPU for inexistent intrinsic methods 2018-05-23 00:27:48 -03:00
gdkchan 173c3e616d Add scalar variants of FCVTZS/FCVTZU, fix a issue on Ryushader 2018-05-18 14:44:49 -03:00
gdkchan 1aa96453ef Add intrinsics support (#121) 
* Initial intrinsics support

* Update tests to work with the new Vector128 type and intrinsics

* Drop SSE4.1 requirement

* Fix copy-paste mistake
 2018-05-11 20:10:27 -03:00
gdkchan 428360c5ac NvServices refactoring (#120) 
* Initial implementation of NvMap/NvHostCtrl

* More work on NvHostCtrl

* Refactoring of nvservices, move GPU Vmm, make Vmm per-process, refactor most gpu devices, move Gpu to Core, fix CbBind

* Implement GetGpuTime, support CancelSynchronization, fix issue on InsertWaitingMutex, proper double buffering support (again, not working properly for commercial games, only hb)

* Try to fix perf regression reading/writing textures, moved syncpts and events to a UserCtx class, delete global state when the process exits, other minor tweaks

* Remove now unused code, add comment about probably wrong result codes
 2018-05-07 15:53:23 -03:00
LDj3SNuD f9b17f86c1 Add Sqxtn_S, Sqxtn_V, Uqxtn_S, Uqxtn_V instructions and Tests (6). (#110) 
* Update ILGeneratorEx.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update CpuTest.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdArithmetic.cs
 2018-04-29 20:39:58 -03:00
LDj3SNuD 3f3844583f Update AOpCodeTable.cs (#108) 2018-04-25 23:26:41 -03:00
LDj3SNuD 966f6b7203 Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104) 
* Update AOpCodeTable.cs

* Update AInstEmitSimdLogical.cs

* Update AInstEmitSimdArithmetic.cs

* Update ASoftFallback.cs

* Update AInstEmitAlu.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs
 2018-04-25 23:20:22 -03:00
gdkchan 27ed5ed039 Improved logging (#103) 2018-04-24 15:57:39 -03:00
gdkchan d45a67fd36 Print guest stack trace on a few points that can throw exceptions 2018-04-22 02:48:17 -03:00
gdkchan 28f7c6decf Stub a few services, add support for generating call stacks on the CPU 2018-04-22 01:22:46 -03:00
LDj3SNuD 9c43b14421 Fix Addp_S in AOpCodeTable. Add 5 Tests: ADDP (scalar), ADDP (vector), ADDV. (#96) 
* Update AOpCodeTable.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update Instructions.cs

* Revert "Started to work in improving the sync primitives"
 2018-04-21 16:15:04 -03:00
LDj3SNuD bc4ada20c7 Add ADDHN{2}, RADDHN{2}, SUBHN{2}, RSUBHN{2} (vector) instructions. Add 8 Tests. (#92) 
* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update Bits.cs

* Create CpuTestSimd.cs

* Create CpuTestSimdReg.cs

* Update CpuTestSimd.cs

Provide a better supply of input values for the 20 Simd Tests.

* Update CpuTestSimdReg.cs

Provide a better supply of input values for the 20 Simd Tests.

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs
 2018-04-20 12:40:15 -03:00
gdkchan 76c1d1440c Add SvcSetThreadActivity, tweak SignalProcessWideKey, add fmul32i shader instructions and other small fixes 2018-04-19 16:18:30 -03:00
MS-DOS1999 b0368079fb Fix Fmin/max and add vector version, add and modifying fmin/max tests (#89) 2018-04-19 00:22:12 -03:00
LDj3SNuD 5a383d86b1 Add ABS (scalar & vector), ADD (scalar), NEG (scalar) instructions. (#88) 
* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update AOpCodeTable.cs
 2018-04-18 10:56:27 -03:00
LDj3SNuD 16660f177e Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). (#77) 
* Update AOpCodeTable.cs

* Update AInstEmitSimdMove.cs

* Update CpuTestSimdMove.cs

* Update AInstEmitSimdMove.cs

* Update CpuTestSimdMove.cs
 2018-04-12 11:52:00 -03:00
gdkchan ef15431613 [CPU] Speed up translation a little bit 2018-04-11 14:44:03 -03:00
gdkchan 2afc12c4a7 [CPU] Fix CNT instruction 2018-04-10 20:58:32 -03:00
LDj3SNuD 65c490f350 Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vector) instructions. Add 5 simple tests. (#74) 
* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdHelper.cs

* Update CpuTestSimdArithmetic.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs
 2018-04-08 16:08:57 -03:00
gdkchan c3a48b8f5c [CPU] Fix CBZ/CBNZ with 32 bits operands 2018-04-06 17:22:26 -03:00
gdkchan 137eb89fad [CPU] Fail early when the index/size of the vector is invalid 2018-04-06 15:39:39 -03:00
gdkchan 6282fe6607 Fix FRSQRTS and FCM* (scalar) instructions 2018-04-06 10:20:17 -03:00
gdkchan 35ff142104 Add FMLS (vector) instruction 2018-04-06 01:41:54 -03:00
gdkchan b73b522835 Add FRSQRTS and FCM* instructions 2018-04-05 23:28:12 -03:00
Merry c4c247deb4 Implement Frsqrte_S (#72) 
* Implement Frsqrte_S

* Implement Frsqrte_V

* Add Frsqrte_S test
 2018-04-05 20:36:19 -03:00
gdkchan ee98d50e17 Add Faddp (vector) instruction 2018-04-04 22:13:10 -03:00
gdkchan 6647e9b749 HashSet is not thread safe, hopefully this fixes the CPU issue where it throws a exception on Add 2018-04-04 18:17:37 -03:00
gdkchan 5c565ff1be Add PRFM (unscaled) instruction 2018-04-04 18:10:20 -03:00
gdkchan 9037055c10 Add FNEG (vector) instruction 2018-04-04 16:36:07 -03:00
gdkchan ce9ccfd1cc Fix 32-bits extended register instructions with 64-bits extensions 2018-03-30 23:32:06 -03:00
gdkchan 67184bcff7 Enable all ld/st (single structure) instructions 2018-03-30 18:06:02 -03:00
gdkchan 6cb940049d Fix EXT/Widening instruction carrying garbage values on some cases, fix ABD (it shouldn't accumulate, this is another variation of the instruction) 2018-03-30 17:37:31 -03:00
gdkchan 94b3eb96a9 Add BIT instruction 2018-03-30 16:46:00 -03:00
gdkchan e580ef1bcf Add UABD instruction 2018-03-30 16:30:23 -03:00
gdkchan 7423ff43a5 Add UABDL instruction 2018-03-30 16:16:16 -03:00
gdkchan 442904a5ed Add UADDL instruction 2018-03-30 15:55:28 -03:00
gdkchan 0a7aaa345c Add UHADD instruction 2018-03-30 12:37:07 -03:00