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target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()

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Backports 1989205c4e973bc7f9fac0ce0700993f30582538
This commit is contained in:
Frank Chang 2021-03-08 12:12:34 -05:00 committed by Lioncash
parent d75c8e7fcf
commit 98982dbe49
1 changed files with 1 additions and 1 deletions
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2
qemu/target/riscv/insn_trans/trans_rvv.inc.c
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@ -950,7 +950,7 @@ static void gen_vec_rsub8_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
static void gen_vec_rsub16_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) static void gen_vec_rsub16_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{ {
tcg_gen_vec_sub8_i64(s, d, b, a); tcg_gen_vec_sub16_i64(s, d, b, a);
} }
static void gen_rsub_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) static void gen_rsub_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)