8 commits

Author	SHA1	Message	Date
Richard Henderson	d1ad8bf44c	target/riscv: Add checks for several RVC reserved operands ... C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved operands that were not diagnosed. Backports commit 4cc16b3b9282e04fab8e84d136540757e82af019 from qemu	2019-05-28 19:20:36 -04:00
Richard Henderson	a62b4e5def	target/riscv: Split RVC32 and RVC64 insns into separate files ... This eliminates all functions in insn_trans/trans_rvc.inc.c, so the entire file can be removed. Backports commit 0e68e240a9bd3b44a91cd6012f0e2bf2a43b9fe2 from qemu	2019-05-28 19:00:23 -04:00
Richard Henderson	a968769d26	target/riscv: Use pattern groups in insn16.decode ... This eliminates about half of the complicated decode bits within insn_trans/trans_rvc.inc.c. Backports commit c2cfb97c01a3636867c1a4a24f8a99fd8c6bed28 from qemu	2019-05-28 18:55:28 -04:00
Richard Henderson	8360c1fa3b	target/riscv: Merge argument decode for RVC shifti ... Special handling for IMM==0 is the only difference between RVC shifti and RVI shifti. This can be handled with !function. Backports commit 6cafec92f1c862a9754ef6a28be68ba7178a284d from qemu	2019-05-28 18:52:50 -04:00
Richard Henderson	dc087c4c0c	target/riscv: Merge argument sets for insn32 and insn16 ... In some cases this allows us to directly use the insn32 translator function. In some cases we still need a shim. Backports commit e1d455dd91c935c714412dafeb24db947429a929 from qemu	2019-05-28 18:50:48 -04:00
Bastian Koppelmann	580457a1d2	target/riscv: Convert quadrant 2 of RVXC insns to decodetree ... Backports commit 97b0be81f6f20bfd53725cb2500b47c6786be532 from qemu	2019-03-19 04:53:07 -04:00
Bastian Koppelmann	b4854e3340	target/riscv: Convert quadrant 1 of RVXC insns to decodetree ... Backports commit 07b001c6fc500fa0e87fd8210f270d7dc8aff9ea from qemu	2019-03-19 04:50:08 -04:00
Lioncash	8d294a7897	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	2019-03-19 04:45:53 -04:00