Commit graph

927 commits

Author SHA1 Message Date
Lioncash 787fd448b1
arm: Move cpu_V1 to DisasContext 2018-10-06 03:28:42 -04:00
Lioncash 1aa20da917
arm: Move cpu_V0 to DisasContext 2018-10-06 03:26:52 -04:00
Lioncash 06c21baaa4
arm: Move cpu_F1d to DisasContext 2018-10-06 03:11:54 -04:00
Lioncash 5f3dd68f9c
arm: Move cpu_F0d to DisasContext 2018-10-06 03:07:42 -04:00
Lioncash e457ce8ccc
arm: Move cpu_F1s to DisasContext 2018-10-06 03:02:06 -04:00
Lioncash a4f23de55f
arm: Move cpu_F0 to DisasContext
Decreases the size of the TCGContext struct for targets that don't need
to use this variable.
2018-10-06 02:58:11 -04:00
Lioncash a61df86ef5
m68k/translate: Remove commented out code in m68k_tcg_init()
This isn't even in the main qemu repo, so we can get rid of this.
2018-10-06 02:41:09 -04:00
Pavel Dovgalyuk 461fbaa9eb
target/i386: fix translation for icount mode
This patch fixes the checking of boundary crossing instructions.
In icount mode only first instruction of the block may cross
the page boundary to keep the translation deterministic.
These conditions already existed, but compared the wrong variable.

Backports commit 41d54dc09f1f327dedc79d5ba0b1b437ab7b0e94 from qemu
2018-10-04 04:32:26 -04:00
Paolo Bonzini 752aea8379
target/i386: rename HF_SVMI_MASK to HF_GUEST_MASK
This flag will be used for KVM's nested VMX migration; the HF_GUEST_MASK name
is already used in KVM, adopt it in QEMU as well.

Backports commit f8dc4c645ec2956a6cd97e0ca0fdd4753181f735 from qemu
2018-10-04 04:24:39 -04:00
Paolo Bonzini 0bc0ff320c
target/i386: unify masking of interrupts
Interrupt handling depends on various flags in env->hflags or env->hflags2,
and the exact detail were not exactly replicated between x86_cpu_has_work
and x86_cpu_exec_interrupt. Create a new function that extracts the
highest-priority non-masked interrupt, and use it in both functions.

Backports commit 92d5f1a4147c3722b5e9a8bcfb7dc261b7a8b855 from qemu
2018-10-04 04:19:57 -04:00
Emilio G. Cota b9bb6cead9
target/i386: move x86_64_hregs to DisasContext
And convert it to a bool to use an existing hole
in the struct.

Backports commit 1dbe15ef57abdf7b6a26c8e638abf6413a4b9d0c from qemu
2018-10-04 04:02:50 -04:00
Emilio G. Cota 90e189ca24
target/i386: move cpu_tmp1_i64 to DisasContext
Backports commit 776678b2961848a80387509c433dc04b0f761592 from qemu
2018-10-04 03:59:13 -04:00
Emilio G. Cota 04530acab2
target/i386: move cpu_tmp3_i32 to DisasContext
Backports commit 4f82446de695f080ed148a0e47fc141e928665af from qemu
2018-10-04 03:56:05 -04:00
Emilio G. Cota 781e6bde41
target/i386: move cpu_tmp2_i32 to DisasContext
Backports commit 6bd48f6f206b6f32a5bbeebc3ae6886d4f587981 from qemu
2018-10-04 03:53:31 -04:00
Emilio G. Cota c13337d1bc
target/i386: move cpu_ptr1 to DisasContext
Backports commit 6387e8303ffb26cfb40b0f93372f1519229b4d2c from qemu
2018-10-04 03:48:09 -04:00
Emilio G. Cota 3e442d4480
target/i386: move cpu_ptr0 to DisasContext
Backports commit 2ee2646491a293a92d1c85e90e12419a8c199ed0 from qemu
2018-10-04 03:46:53 -04:00
Emilio G. Cota cc872aa711
target/i386: move cpu_tmp4 to DisasContext
Backports commit 5022f28f1e4033eb369b744ad61b96d086beca1b from qemu
2018-10-04 03:45:28 -04:00
Emilio G. Cota d2752ebc42
target/i386: move cpu_tmp0 to DisasContext
Backports commit fbd80f02df3fe272ba0f4825df27b8459dafbc14 from qemu
2018-10-04 03:41:13 -04:00
Emilio G. Cota b704b6c205
target/i386: move cpu_T1 to DisasContext
Backports commit b48597b0eda32d4c7ade2ba3f98f06f62289e3e2 from qemu
2018-10-04 03:35:10 -04:00
Emilio G. Cota 70b327dc82
target/i386: move cpu_T0 to DisasContext
Backports commit c66f97273f677d76afaaeb0e688eb08499701b1b from qemu
2018-10-04 03:29:13 -04:00
Emilio G. Cota c1d70758ea
target/i386: move cpu_A0 to DisasContext
Backports commit 6b672b5d6b14422c131969c5725f738751e12847 from qemu
2018-10-04 01:16:35 -04:00
Emilio G. Cota 30c66bcca3
target/i386: move cpu_cc_srcT to DisasContext
Backports commit 93a3e108eb6a9bb781ab7db6e92d91528e482030 from qemu
2018-10-04 00:59:00 -04:00
Peter Maydell 04fead0dcb
target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode
The ARMv8 architecture defines that an AArch32 CPU starts
in SVC mode, unless EL2 is the highest available EL, in
which case it starts in Hyp mode. (In ARMv7 a CPU with EL2
but not EL3 was not a valid configuration, but we don't
specifically reject this if the user asks for one.)

Backports commit 060a65df056a5d6ca3a6a91e7bf150ca1fbccddf from qemu
2018-09-25 21:19:44 -04:00
Richard Henderson 994038c817
target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs
Not only are the sve-related tb_flags fields unused when SVE is
disabled, but not all of the cpu registers are initialized properly
for computing same. This can corrupt other fields by ORing in -1,
which might result in QEMU crashing.

This bug was not present in 3.0, but this patch is cc'd to
stable because adf92eab90e3f5f34c285 where the bug was
introduced was marked for stable.

Backports commit e79b445d896deb61909be52b61b87c98a9ed96f7 from qemu
2018-09-25 21:17:32 -04:00
Andrew Dutcher 81f8a1be80
eflags patch
Preserves EFLAGS across basic blocks.

Reapplies commit 3a1f231e8f from qemu
2018-09-07 22:01:24 -04:00
vardyh 8ca718367f
x86::trans: handle illegal case for opc c6/c7
Reference Intel software developer manual vol2 Appendix A Table A-6 for
detailed decoding information.

Re-applies commit ad767abda8 from qemu
2018-09-07 19:28:01 -04:00
Lioncash fa8f566635
target/mips/cpu: Use type_register instead of type_register_static() in mips_cpu_register_types()
The lifetime of the TypeInfo instance doesn't live indefinitely, so we
should be using the regular type_register().
2018-09-03 17:36:23 -04:00
Lioncash e81fa596bc
target/arm/cpu: Use type_register instead of type_register_static() in arm_cpu_register_types()
The lifetime of the TypeInfo instance doesn't live indefinitely, so we
should be using the regular type_register().
2018-09-03 17:34:08 -04:00
Lioncash 34b22968a4
target/i386/cpu: Use type_register instead of type_register_static in x86_cpu_register_types()
The lifetime of the TypeInfo instance doesn't live indefinitely, so we
should be using the regular type_register().
2018-09-03 17:28:54 -04:00
Lioncash 0a759bf7f3
target/sparc: Fix SPARC target initialization
Brings up the SPARC target so it's able to be used for emulation
purposes.
2018-09-03 17:26:00 -04:00
Lioncash 44ca501cd3
target/m68k: Fix initialization of m68k targets
m68k is now able to be used for emulation again. It just needed to
properly have the unicorn context be set within the base type for the
CPUs
2018-09-03 17:04:42 -04:00
MerryMage 9b87d0f61a unicorn_arm: Allow for read/write of UC_ARM_REG_FPSCR 2018-09-03 21:03:55 +01:00
Lioncash fffc31e7e2
target/i386/translate: Synchronize EIP if read/write callbacks are set
This is another feature that was left by the wayside when upgrading
qemu. It's fairly trivial to restore.
2018-09-03 14:40:46 -04:00
Lioncash 0d0d8b6db9
target/i386/translate: Report proper instruction size in code hooks
This was intentionally broken to make updating qemu as quick as possible
when it was woefully out of date, particularly because the interface of
qemu's TCG changed quite a bit, so this code would have needed to be
changed anyways.

Now that qemu is up to date for this variant of Unicorn, we can repair
this functionality and also--and I put massive emphasis on this, since
this wasn't done in the original Unicorn repo--*actually document what
the heck we're doing in this case*, so it's not a pain to change in the
future if we actually need to do that. It makes it much, much, simpler
for people not involved with qemu to understand what is going on in this
case.
2018-09-03 14:09:05 -04:00
Lioncash dce6dde483
target/i386/translate: Remove unnecessary (and incorrect) pointer casts from some gen_op functions
These used to be necessary, as the relevant variables used to be void*,
thus making the casts necessary. Given they were changed to concrete
types over the course of backporting, these are unnecessary.
2018-09-03 10:44:55 -04:00
Lioncash 2beb139304
i386: Fix initialization of x86 targets 2018-09-03 09:14:35 -04:00
Nguyen Anh Quynh d149648f2f
x86: fix #968. also fix potential bug of not clearing high bytes when updateing EIP
Backports commit 4d0157eb4a4891fe9101ac84accbd11cd4277794 from qemu
2018-09-03 07:58:16 -04:00
toshiMSFT b4bb7edfe8
Makes SYSENTER hookable again on x86
Adds SYSENTER to the whitelist of supported hookable instructions in unicorn
as well as fixes up the existing sysenter_hook_x86 regression test which was
previously failing

Fixes unicorn-engine/unicorn#995

Backports commit 0f14c473445661a633ca5bda3a91ba1a87c35c64 from unicorn
2018-09-03 07:53:48 -04:00
MerryMage a13d51f756 unicorn_aarch64: Use aa64_vfp_qreg instead of aa32_vfp_dreg 2018-09-03 07:47:40 +01:00
MerryMage 896a8e1320 unicorn_arm: Use ARM offset not ARM64 offset
Was introduced by 5439b4a542
2018-09-03 07:44:29 +01:00
Stefan Markovic c870339a10
target/mips: Add definition of nanoMIPS I7200 CPU
Add definition of the first nanoMIPS processor in QEMU.

Backports commit d45942d908edee175a90f915ab92ac302eedf33a from qemu
2018-08-27 15:08:12 -04:00
Yongbok Kim d53c021cea
target/mips: Fix ERET/ERETNC behavior related to ADEL exception
Fix ERET/ERETNC so that ADEL exception can be raised.

Backports commit 26324ded91a5ad08a5de8f32b8ed5e5e243154cf from qemu
2018-08-27 15:00:59 -04:00
Stefan Markovic 7473e6dbe6
target/mips: Add updating BadInstr and BadInstrX for nanoMIPS
Update BadInstr and BadInstrX registers for nanoMIPS. The same
support for pre-nanoMIPS remains unimplemented.

Backports commit 7a5f784aa215df6bf5d674b4003f8df43bf3b2d4 from qemu
2018-08-27 15:00:05 -04:00
Dimitrije Nikolic 7e0342c9f6
target/mips: Add availability control via bit NMS
A set of nanoMIPS instructions is not available if Config5 bit NMS
is set.

Backports commit fb32f8c8560be7ca4e323cee1b839701126401d1 from qemu
2018-08-27 14:59:15 -04:00
Stefan Markovic 38f2640a34
target/mips: Add emulation of DSP ASE for nanoMIPS - part 6
Add emulation of DSP ASE instructions for nanoMIPS - part 6.

Backports commit 0b591184a2d0686b8f2c5fb27cc9fe2f60752d57 from qemu
2018-08-27 06:47:59 -04:00
Stefan Markovic ba7d8bc0ab
target/mips: Add emulation of DSP ASE for nanoMIPS - part 5
Add emulation of DSP ASE instructions for nanoMIPS - part 5.

Backports commit 4c75c985d9b4d2ac7e0183083e31c243b06a3f2b from qemu
2018-08-27 06:45:25 -04:00
Stefan Markovic 73a5efd599
target/mips: Add emulation of DSP ASE for nanoMIPS - part 4
Add emulation of DSP ASE instructions for nanoMIPS - part 4.

Backports commit 8b3698b2947610e0645a65ace4822164d55dd76b from qemu
2018-08-27 06:43:34 -04:00
Stefan Markovic b6602fff1f
target/mips: Add emulation of DSP ASE for nanoMIPS - part 3
Add emulation of DSP ASE instructions for nanoMIPS - part 3.

Backports commit 2ed42efaae9516b71b7edf669b120cad718ba37b from qemu
2018-08-27 06:34:14 -04:00
Stefan Markovic 33dee2e5f3
target/mips: Add emulation of DSP ASE for nanoMIPS - part 2
Add emulation of DSP ASE instructions for nanoMIPS - part 2.

Backports commit 6d033ca7513d85562f1b6bbb002a38b1c2541e5d from qemu
2018-08-27 05:53:17 -04:00
Stefan Markovic 49f448af3c
target/mips: Add emulation of DSP ASE for nanoMIPS - part 1
Add emulation of DSP ASE instructions for nanoMIPS - part 1.

Backports commit 3285a3e4445be70d5f2dbdd29249e1e2627a5216 from qemu
2018-08-27 05:52:12 -04:00