11 commits

Author	SHA1	Message	Date
LIU Zhiwei	965af9986a	target/riscv: vector integer comparison instructions ... 1366fc79be04fa56a0e3f078ba4f26c27ac67e89	2021-02-26 10:40:33 -05:00
LIU Zhiwei	244793c4e8	target/riscv: vector single-width bit shift instructions ... Backports 3277d955d21d8943d80062b4cfd8547f831dbd51	2021-02-26 10:37:09 -05:00
LIU Zhiwei	56c0e253c2	target/riscv: vector bitwise logical instructions ... Backports d3842924cf93d104f691c5ea9090d6700ccef281	2021-02-26 10:30:33 -05:00
LIU Zhiwei	05153c6d7c	target/riscv: vector integer add-with-carry / subtract-with-borrow instructions ... 3a6f8f68ad2f4a22d9ae8287f336b5dcc80b6448	2021-02-26 10:19:48 -05:00
LIU Zhiwei	b9814de4c3	target/riscv: vector widening integer add and subtract ... Backports 8fcdf77630290591a6068c2d82ca2935338c3b0c	2021-02-26 10:05:43 -05:00
LIU Zhiwei	f564388e89	target/riscv: vector single-width integer add and subtract ... Backports 43740e3a3b3bb66456103684e622ba4e9baae297	2021-02-26 09:58:31 -05:00
LIU Zhiwei	7d0d7338c2	target/riscv: add vector amo operations ... Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Backports 268fcca66bde62257960ec8d859de374315a5e3d	2021-02-26 09:47:32 -05:00
LIU Zhiwei	152934bade	target/riscv: add fault-only-first unit stride load ... The unit-stride fault-only-fault load instructions are used to vectorize loops with data-dependent exit conditions(while loops). These instructions execute as a regular load except that they will only take a trap on element 0. Backports commit 022b4ecf775ffeff522eaea4f0d94edcfe00a0a9 from qemu	2021-02-26 09:28:19 -05:00
LIU Zhiwei	887c29bc79	target/riscv: add vector index load and store instructions ... Vector indexed operations add the contents of each element of the vector offset operand specified by vs2 to the base effective address to give the effective address of each element. Backports f732560e3551c0823cee52efba993fbb8f689a36	2021-02-26 03:00:45 -05:00
LIU Zhiwei	c7a17d04a2	target/riscv: add vector stride load and store instructions ... Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Backports 751538d5da557e5c10e5045c2d27639580ea54a7	2021-02-26 02:55:14 -05:00
LIU Zhiwei	9db3b70869	target/riscv: add vector configure instruction ... vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Backports 2b7168fc43fb270fb89e1dddc17ef54714712f3a from qemu	2021-02-26 02:37:59 -05:00