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981 commits

Author SHA1 Message Date
Richard Henderson a5ac288135
tcg: Remove gen_intermediate_code_pc
It is no longer used, so tidy up everything reached by it.
This includes the gen_opc_* arrays, the search_pc parameter
and the inline gen_intermediate_code_internal functions.

Backports commit 4e5e1215156662b2b153255c49d4640d82c5568b from qemu
2018-02-17 15:23:59 -05:00
Richard Henderson 66de6cc37c
tcg: Save insn data and use it in cpu_restore_state_from_tb
We can now restore state without retranslation.

Backports commit fca8a500d519a56abeaedf8073167a61d3c6b9c4 from qemu
2018-02-17 15:23:59 -05:00
Richard Henderson a7cf761caf
tcg: Merge cpu_gen_code into tb_gen_code
As it's only caller, this tidies things a bit.

Backports commit fec88f64bda27846add83e924c8f4def9d94e068 from qemu
2018-02-17 15:23:59 -05:00
Paolo Bonzini 268275f04b
translate: check cflags instead of use_icount global
Backports applicable parts of commit bd79255d2571a3c68820117caf94ea9afe1d527e
2018-02-17 15:23:59 -05:00
Paolo Bonzini cab4c979f0
cpu-exec: add a new CF_USE_ICOUNT cflag
Backports commit 0266359e57987d6be53fbcb885f2dd39c1dae940 from qemu
2018-02-17 15:23:58 -05:00
Pavel Dovgalyuk ac46898b3c
cpu-exec: invalidate nocache translation if they are interrupted
In this case, QEMU might longjmp out of cpu-exec.c and miss the final
cleanup in cpu_exec_nocache.  Do this manually through a new compile
flag.

Backports commit d8a499f17ee5f05407874f29f69f0e3e3198a853 from qemu
2018-02-17 15:23:58 -05:00
Richard Henderson 1cbd175736
tcg: Pass data argument to restore_state_to_opc
The gen_opc_* arrays are already redundant with the data stored in
the insn_start arguments. Transition restore_state_to_opc to use
data from the latter.

Backports commit bad729e272387de7dbfa3ec4319036552fc6c107 from qemu
2018-02-17 15:23:58 -05:00
Lioncash b115c5509d
tcg: Add TCG_MAX_INSNS
Adjust all translators to respect it.

Backports commit 190ce7fbc79fd0883a6170d7f30da59d366e6830 from qemu
2018-02-17 15:23:58 -05:00
Lioncash f8d54a8f3c
Drop unused crypto source files 2018-02-17 15:23:57 -05:00
Richard Henderson 5637099383
target-*: Drop cpu_gen_code define
This symbol no longer exists.

Backports commit dc03246cc377268db63abc8c5663ef571aec2eea from qemu
2018-02-17 15:23:57 -05:00
Richard Henderson 25e0621757
target-sparc: Add npc state to insn_start
Backports commit a3d5ad761cafc669e25f4185e63d8d758a989135 from qemu
2018-02-17 15:23:57 -05:00
Richard Henderson 2c1ae7a408
target-sparc: Remove gen_opc_jump_pc
Since jump_pc[1] is always npc + 4, we can infer after incrementing
that jump_pc[1] == pc + 4. Because of that, we can encode the branch
destination into a single word, and store that in npc.

Backports commit 6c42444f9a53b6af39d46008cb9f650b11e96cb9 from qemu
2018-02-17 15:23:56 -05:00
Richard Henderson b709d15b13
target-sparc: Split out gen_branch_n
Unify three copies of this code from different
branch types. Fix the case when npc == DYNAMIC_PC,
i.e. a branch within a delay slot.

Backports commit 2bf2e019ed0a6349220620240c0ba807846793b9 from qemu
2018-02-17 15:23:56 -05:00
Richard Henderson ee918c940c
target-sparc: Tidy gen_branch_a interface
We always pass pc2 == dc->npc and r_cond == cpu_cond,
and always set is_br afterward. Infer all of that.

Backports commit bfa31b765798139804ce9e5e35c7e142d233df31 from qemu
2018-02-17 15:23:56 -05:00
Richard Henderson f05c35c49c
target-i386: Add cc_op state to insn_start
Backports commit 2066d09516ba34d0d180fdea451436d9babb3308 from qemu
2018-02-17 15:23:56 -05:00
Richard Henderson 500e116581
target-mips: Add delayed branch state to insn_start
Backports commit c20d594e45bc8c4b21be1a7637cba0f279f72879 from qemu
2018-02-17 15:23:56 -05:00
Paolo Bonzini 96e0535c76
target-i386: add ABM to Haswell* and Broadwell* CPU models
ABM is only implemented as a single instruction set by AMD; all AMD
processors support both instructions or neither. Intel considers POPCNT
as part of SSE4.2, and LZCNT as part of BMI1, but Intel also uses AMD's
ABM flag to indicate support for both POPCNT and LZCNT. It has to be
added to Haswell and Broadwell because Haswell, by adding LZCNT, has
completed the ABM.

Tested with "qemu-kvm -cpu Haswell-noTSX,enforce" (and also with older
machine types) on an Haswell-EP machine.

Backports commit becb66673ec30cb604926d247ab9449a60ad8b11 from qemu
2018-02-17 15:23:55 -05:00
Bill Paul 5b14f0ed52
Correctly re-init EFER state during INIT IPI
When doing a re-initialization of a CPU core, the default state is to _not_
have 64-bit long mode enabled. This means the LME (long mode enable) and LMA
(long mode active) bits in the EFER model-specific register should be cleared.

However, the EFER state is part of the CPU environment which is
preserved by do_cpu_init(), so if EFER.LME and EFER.LMA were set at the
time an INIT IPI was received, they will remain set after the init completes.

This is contrary to what the Intel architecture manual describes and what
happens on real hardware, and it leaves the CPU in a weird state that the
guest can't clear.

To fix this, the 'efer' member of the CPUX86State structure has been moved
to an area outside the region preserved by do_cpu_init(), so that it can
be properly re-initialized by x86_cpu_reset().

Backports commit 2188cc52cb363433751f72b991d8fb05fc60e39d from qemu
2018-02-17 15:23:55 -05:00
Lioncash da8e73b887
qom/cpu: Add throttle_thread_scheduled member
Extracts the member out of commit 2adcc85d407c1ab985f5abed808c78dbb84f4773
2018-02-17 15:23:55 -05:00
Peter Crosthwaite 1faea35feb
i386: Rename ELF_MACHINE to be x86 specific
Rename ELF_MACHINE to be I386 specific. This is used as-is by the
multiboot loader.

Linux-user previously used this definition but will not anymore,
falling back to the default bahaviour of using ELF_ARCH as ELF_MACHINE.

This removes another architecture specific definition from the global
namespace.

Backports commit a5e8788f89312f19f54dba0454ee5bf7209b4cd7 from qemu
2018-02-17 15:23:55 -05:00
Peter Crosthwaite 95bcb2f144
mips: Remove ELF_MACHINE from cpu.h
The only generic code relying on this is linux-user, but linux users'
default behaviour of defaulting ELF_MACHINE to ELF_ARCH will handle
this.

The bootloaders can just pass EM_MIPS directly, as that is
architecture specific code.

This removes another architecture specific definition from the global
namespace.

Backports commit 04ce380e9e3fad1dbf4e86ebdf9315573a06b30e from qemu
2018-02-17 15:23:55 -05:00
Peter Crosthwaite 23dc795806
sparc: Remove ELF_MACHINE from cpu.h
The bootloaders can just pass EM_SPARC or EM_SPARCV9 directly, as
they are architecture specific code (to one or the other).

This removes another architecture specific definition from the global
namespace.

Backports commit 77452383e0c45704e2339b58eac29a3730bc18b1 from qemu
2018-02-17 15:23:55 -05:00
Peter Crosthwaite b848c7a51f
m68k: Remove ELF_MACHINE from cpu.h
The only generic code relying on this is linux-user, but linux users'
default behaviour of defaulting ELF_MACHINE to ELF_ARCH will handle
this.

The machine model bootloaders can just pass EM_68K directly, as that
is architecture specific code.

This removes another architecture specific definition from the global
namespace.

Backports commit 45e6b8b61a7bbb71d1fa6c4193b47ba3a1f9f033 from qemu
2018-02-17 15:23:54 -05:00
Peter Crosthwaite 9f8b8ba793
arm: Remove ELF_MACHINE from cpu.h
The only generic code relying on this is linux-user. Linux user
already has a lot of #ifdef TARGET_ customisation so instead, define
ELF_ARCH as either EM_ARM or EM_AARCH64 appropriately.

The armv7m bootloader can just pass EM_ARM directly, as that
is architecture specific code. Note that arm_boot already has its own
logic selecting an arm specific elf machine so this makes V7M more
consistent with arm_boot.

This removes another architecture specific definition from the global
namespace.

Backports commit b597c3f7da17fcb37d394a16a6c0ef0a02846177 from qemu
2018-02-17 15:23:54 -05:00
Pavel Butsykin 96f8d6325a
apic_internal.h: fix formatting and drop unused consts
Fix formatting of local apic definitions and drop unused constant
APIC_INPUT_POLARITY, APIC_SEND_PENDING. Magic numbers in shifts are
replaced with constants defined just above.

Backports commit b6cfc3c2ac5a1025d8fe7d74421a73ec495408f9 from qemu
2018-02-17 15:23:54 -05:00
Pavel Butsykin 79559c82aa
apic_internal.h: rename ESR_ILLEGAL_ADDRESS to APIC_ESR_ILLEGAL_ADDRESS
Added prefix APIC_ for determining the constant of a particular subsystem,
improve the overall readability and match other constant names.

Backports commit a22bf99c5852f369dc620be2c3c93535a5b69a58 from qemu
2018-02-17 15:23:54 -05:00
Pavel Butsykin fcd3e3e449
apic_internal.h: added more constants
These constants are needed for optimal access to
bit fields local apic registers without magic numbers.

Backports commit 6519d187e301c5a14a8c9b32fb93027b04a4336d from qemu
2018-02-17 15:23:54 -05:00
Aurelien Jarno b5f5e2dbc2
tcg/mips: pass oi to tcg_out_tlb_load
Instead of computing mem_index and s_bits in both tcg_out_qemu_ld and
tcg_out_qemu_st function and passing them to tcg_out_tlb_load, directly
pass oi to the tcg_out_tlb_load function and compute mem_index and
s_bits there.

Backports commit 81dfaf1a8f7f95259801da9732472f879023ef77 from qemu
2018-02-17 15:23:54 -05:00
Eric Blake b78bb417eb
error: Copy location information in error_copy()
Commit 1e9b65bb forgot to propagate source information to copied
errors.

Backports commit 88e2ce291595ed8f12636b40523fdb215a9d3374 from qemu
2018-02-17 15:23:53 -05:00
Pavel Dovgaluk 011861cd0e
target-mips: improve exception handling
This patch improves exception handling in MIPS.
Instructions generate several types of exceptions.
When exception is generated, it breaks the execution of the current
translation block. Implementation of the exceptions handling does not
correctly restore icount for the instruction which caused the exception.
In most cases icount will be decreased by the value equal to the size of
TB. This patch passes pointer to the translation block internals to the
exception handler. It allows correct restoring of the icount value.

Backports commit 9c708c7f9fbb813a3fac02f2728e51e62f2f5ffc from qemu
2018-02-17 15:23:53 -05:00
Leon Alrae 2a968bb547
target-mips: correct MTC0 instruction on MIPS64
MTC0 on a 64-bit processor should move entire 64-bit GPR content to CP0
register.

Backports commit d54a299b83a07642c85a22bfe19b69ca4def9ec4 from qemu
2018-02-17 15:23:53 -05:00
Leon Alrae 18dcbc7a64
target-mips: add missing restriction in DAUI instruction
rs cannot be the zero register, Reserved Instruction exception must be
signalled for this case.

Backports commit db77d8523909b32d798cd2c80de422b68f9e5c42 from qemu
2018-02-17 15:23:53 -05:00
Aurelien Jarno 1a441096c0
target-mips: get rid of MIPS_DEBUG
MIPS_DEBUG is a define used to dump the instruction disassembling. It
has to be defined at compile time. In practice I believe it's more
efficient to just look at the instruction disassembly and op dump using
-d in_asm,op. This patch therefore removes the corresponding code, which
clutters translate.c.

Backports commit 9d68ac14dab3f5af33a6b23458941dc6fb261fce from qemu
2018-02-17 15:23:52 -05:00
Aurelien Jarno 0045d99f38
target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONS
MIPS_DEBUG_SIGN_EXTENSIONS was used sometimes ago to verify that 32-bit
instructions correctly sign extend their results. It's now not need
anymore, remove it.

Backports commit b307446e04232b3a87e9da04886895a8e5a4a407 from qemu
2018-02-17 15:23:52 -05:00
Alex Smith c48b0f76ee
target-mips: Fix RDHWR on CP0.Count
For RDHWR on the CP0.Count register, env->CP0_Count was being returned.
This value is a delta against the QEMU_CLOCK_VIRTUAL clock, not the
correct current value of CP0.Count. Use cpu_mips_get_count() instead.

Backports commit cdfcad788394ff53e317043e07b8e34f4987c659 from qemu
2018-02-17 15:23:52 -05:00
Petar Jovanovic dfa3d51a0f
target-mips: remove wrong checks for recip.fmt and rsqrt.fmt
Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
they require any particular mode for its FPU. This patch removes the checks
that may break a program that uses these instructions.

Backports commit ca6c7803d2beae43299a80f4549d36579881fc0b from qemu
2018-02-17 15:23:52 -05:00
Peter Crosthwaite afb48e9fc5
cputlb: Change tlb_set_dirty() arg to cpu
Change tlb_set_dirty() to accept a CPU instead of an env pointer. This
allows for removal of another CPUArchState usage from prototypes that
need to be QOMified.

Backports commit bcae01e468d961ad9afaf4148329147e4be209ab from qemu
2018-02-17 15:23:52 -05:00
Peter Crosthwaite 2b15db6e12
tcg: split tcg_op_defs to -common
tcg_op_defs (and the _max) are both needed by the TCI disassembler. For
multi-arch, tcg.c will be multiple-compiled (arch-obj) with its symbols
hidden from common code. So split the definition off to new file,
tcg-common.c which will remain a regular obj-y for use by both the TCI
disas as well as the multiple tcg.c's.

Backports commit 7d8f787d9d261d6880b69e35ed682241e3f9242f from qemu
2018-02-17 15:23:51 -05:00
Peter Crosthwaite 7a004907c7
translate-all: Move tcg_handle_interrupt() to -common
Move this function to common code. It has no arch specific
dependencies. Prepares support for multi-arch where the translate-all
interface needs to be virtualised. One less thing to virtualise.

Backports commit 9b68a7754a892d8deb7696cfe609fe2ec3c6034a from qemu
2018-02-17 15:23:51 -05:00
Peter Crosthwaite bf067fcc26
cpu-exec: Migrate some generic fns to cpu-exec-common
The goal is to split the functions such that cpu-exec is CPU specific
content, while cpus-exec-common.c is generic code only. The function
interface to cpu-exec needs to be virtualised to prepare support for
multi-arch and moving these definitions out saves bloating the QOM
interface. So move these definitions out of cpu-exec to a new module,
cpu-exec-common.

Backports commit 5abf9495ca9ff41160260ac274115825c10545cc from qemu
2018-02-17 15:23:51 -05:00
Paolo Bonzini f1a592f4a1
cpu: initialize cpu->exception_index on reset
This unbreaks linux-user (broken by e511b4d, cpu-exec: reset exception_index
correctly, 2014-11-26).

Backports commit f9d8f6673591f30028e281e8ff6d5790adc2de83 from qemu
2018-02-17 15:23:51 -05:00
Lioncash 5e2862b29d
cpu: Add crash_occurred flag into CPUState
CPUState::crash_occurred field inside CPUState marks
that guest crash occurred. This value is added into
cpu common migration subsection.

Backports commit bac05aa9a77af1ca7972c8dc07560f4daa7c2dfc from qemu
2018-02-17 15:23:51 -05:00
Pavel Dovgalyuk 62544c10af
target-i386: exception handling for other helper functions
This patch fixes exception handling for other helper functions.

Backports commit 4054cdec0423c7190bfc733c27c303d513d531ab from qemu
2018-02-17 15:23:51 -05:00
Pavel Dovgalyuk 08f93c3fe6
target-i386: exception handling for seg_helper functions
This patch fixes exception handling for seg_helper functions.

Backports commit 100ec0991958d0c1b61f140e64dbe92991c6dd2c from qemu
2018-02-17 15:23:50 -05:00
Pavel Dovgalyuk 57b96e16af
target-i386: exception handling for memory helpers
This patch fixes exception handling for memory helpers
and removes obsolete PC update from translate.c.

Backports commit 2afbdf84807d673eb682cb78158e11cdacbf4673 from qemu
2018-02-17 15:23:50 -05:00
Pavel Dovgalyuk 837a36b1e8
target-i386: exception handling for div instructions
This patch fixes exception handling for div instructions
and removes obsolete PC update from translate.c.

Backports commit cc33c5d66bb315f77739f761a3f868a7d138c041 from qemu
2018-02-17 15:23:50 -05:00
Pavel Dovgalyuk afe5ed6f49
target-i386: exception handling for FPU instructions
This patch fixes exception handling for FPU instructions
and removes obsolete PC update from translate.c.

Backports commit 6cad09d2f74d7318f737acaa21b3da49a0c9e670 from qemu
2018-02-17 15:23:50 -05:00
Pavel Dovgalyuk 56615596e4
target-i386: introduce new raise_exception functions
This patch introduces new versions of raise_exception functions
that receive TB return address as an argument.

Backports commit 9198009529d06b6489b68a7505942cca3a50893f from qemu
2018-02-17 15:23:50 -05:00
Daniel P. Berrange 4c726ca49b
crypto: move crypto objects out of libqemuutil.la
Future patches will be adding more crypto related APIs which
rely on QOM infrastructure. This creates a problem, because
QOM relies on library constructors to register objects. When
you have a file in a static .a library though which is only
referenced by a constructor the linker is dumb and will drop
that file when linking to the final executable :-( The only
workaround for this is to link the .a library to the executable
using the -Wl,--whole-archive flag, but this creates its own
set of problems because QEMU is relying on lazy linking for
libqemuutil.a. Using --whole-archive majorly increases the
size of final executables as they now contain a bunch of
object code they don't actually use.

The least bad option is to thus not include the crypto objects
in libqemuutil.la, and instead define a crypto-obj-y variable
that is referenced directly by all the executables that need
this code (tools + softmmu, but not qemu-ga). We avoid pulling
entire of crypto-obj-y into the userspace emulators as that
would force them to link to gnutls too, which is not required.

Backports commit fb37726db77b21f3731b90693d2c93ade1777528 from qemu
2018-02-17 15:23:50 -05:00
Paolo Bonzini 195a86283f
exec: make mmap_lock/mmap_unlock globally available
There is some iffy lock hierarchy going on in translate-all.c. To
fix it, we need to take the mmap_lock in cpu-exec.c. Make the
functions globally available.

Backports commit 8fd19e6cfd5b6cdf028c6ac2ff4157ed831ea3a6 from qemu
2018-02-17 15:23:49 -05:00