106 commits

Author	SHA1	Message	Date
Bastian Koppelmann	11e2b9c410	target/riscv: Convert RVXI arithmetic insns to decodetree ... we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Backports commit b73a987b09ad5081123dc6b1e8e6c8305a1c8673 from qemu	2019-03-18 16:04:49 -04:00
Bastian Koppelmann	1024ceb4df	target/riscv: Convert RV64I load/store insns to decodetree ... this splits the 64-bit only instructions into its own decode file such that we generate the decoder for these instructions only for the RISC-V 64 bit target. Backports commit 7e45a682edc32ba90d6955215f062210531b835b from qemu	2019-03-18 16:02:16 -04:00
Bastian Koppelmann	65a415372b	target/riscv: Convert RV32I load/store insns to decodetree ... Backports commit c1000d4e1bdb13857b601c425aca2fda9131283b from qemu	2019-03-18 15:59:43 -04:00
Bastian Koppelmann	55dc0038e8	target/riscv: Convert RVXI branch insns to decodetree ... Backports commit 3cca75a6fe8b3f85e19559ffa64cb0be370d2814 from qemu	2019-03-18 15:58:16 -04:00
Bastian Koppelmann	5e5b3e9ea9	target/riscv: Activate decodetree and implemnt LUI & AUIPC ... for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Backports commit 2a53cff418335ccb4719e9a94fde55f6ebcc895d from qemu	2019-03-18 15:54:17 -04:00
Lioncash	b6f752970b	target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.	2019-03-08 21:46:10 -05:00