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Author SHA1 Message Date
Nguyen Anh Quynh 6478a24404 Merge branch 'gdt_idt' of https://github.com/cseagle/unicorn into cseagle-gdt_idt 2016-02-06 17:31:42 +08:00
Chris Eagle 49b9f4f8da uc_x86_mmr type available in qemu/target-i386/unicorn.c 2016-02-04 19:09:41 -08:00
Nguyen Anh Quynh 07e8f2f60d Merge pull request #423 from lunixbochs/master 
add regress for #421
 2016-02-05 09:45:01 +08:00
Ryan Hileman bcfa41c90d add regress for #421 2016-02-05 02:35:17 +01:00
Nguyen Anh Quynh 9b6d1bf324 regress: fix compilation warning for mem_fuzz.c 2016-02-05 08:54:52 +08:00
Nguyen Anh Quynh a5d9daaef4 Merge branch 'mem_fuzzing' of https://github.com/eqv/unicorn into eqv-mem_fuzzing 2016-02-05 08:49:18 +08:00
Chris Eagle 59f7bf3be7 file perms 2016-02-04 16:48:27 -08:00
Chris Eagle e59382e030 updated gdtr/idtr/ldtr/tr read/write code 2016-02-04 16:44:52 -08:00
coco 1e13777c91 added memory fuzzer and 2 resulting testcases 2016-02-04 19:57:20 +01:00
Chris Eagle 9977054a15 add support for setting gdtr, idtr, ldtr, and tr programatically 2016-02-03 09:22:29 -08:00
Nguyen Anh Quynh 101f14285a chmod +x arm_init_input_crash.py 2016-02-03 09:20:15 +08:00
McLovi9 ac806d3bfb Create arm_init_input_crash.py 2016-02-02 20:36:36 +01:00
Nguyen Anh Quynh e42aba760f fix a typo in test_tb_x86.c 2016-01-31 14:07:35 +08:00
Nguyen Anh Quynh 32b9deca04 unit: use UC_HOOK_MEM_VALID for test_tb_x86.c 2016-01-31 13:14:11 +08:00
Nguyen Anh Quynh 1fb5416f4a unit: simplify test_tb_x86.c 2016-01-31 13:06:42 +08:00
Nguyen Anh Quynh a5020c69bb Merge pull request #408 from egberts/master 
Pull Request for Issue #364: Invalidating Translation Cache after self-modifying code
 2016-01-31 10:37:04 +08:00
steve fc22a359e2 Issue #364 - Move RIP/PC closer next to the offending self-modifying code 
which modified the 2nd next instruction (imul) in which that escaped
our wonderful ability to invalidate the
instruction translation cache in which we badly need to pick up the
self-modification being made.
 2016-01-30 19:30:17 -05:00
Nguyen Anh Quynh 5a04bcb115 allow to change PC during callback. this solves issue #210 2016-01-28 14:06:17 +08:00
Nguyen Anh Quynh 48ab148d1c Merge branch 'hook' 2016-01-26 22:52:29 +08:00
xorstream 7973f6b4c9 Added mode endian flags for sparc tests and fixed mode in sparc_jump_to_zero.c 2016-01-25 13:50:26 +11:00
xorstream 26d3b1e7d6 Added ppc 32bit mode and added sparc mode checks to bring it in line with other archs 2016-01-24 22:27:33 +11:00
Nguyen Anh Quynh 249e2ac0a0 Merge branch 'hook-refactor' of https://github.com/lunixbochs/unicorn into lunixbochs-hook-refactor 2016-01-23 10:58:37 +08:00
Nguyen Anh Quynh d79925f477 sparc: add SPARC32 mode (= UC_MODE_32) 2016-01-23 10:48:18 +08:00
Ryan Hileman 33180b5afa add test for multiple basic block hooks 2016-01-22 18:42:14 -08:00
Nguyen Anh Quynh 5c6c67bb3a regress: fix Sparc mode for sparc_reg.py 2016-01-23 10:17:42 +08:00
xorstream 8763d426c2 Fix uc_mode usage in source code 2016-01-23 12:08:49 +11:00
Nguyen Anh Quynh 840eb54f05 Revert "arm64: fix the access to tcg_op_defs[] in arm64 backend (issue #387)" 
This reverts commit 3000ca6abf.
 2016-01-22 11:33:36 +08:00
Nguyen Anh Quynh 3000ca6abf arm64: fix the access to tcg_op_defs[] in arm64 backend (issue #387) 2016-01-22 11:33:28 +08:00
Nguyen Anh Quynh 6f0a01293d unit: fix some compilation warnings in test_tb_x86.c 2016-01-17 10:06:00 +08:00
steve f0dac63b69 In response to issue #364, a unit test case has been created 
for exercising proper flushing of the instruction translation cache.
 2016-01-16 18:05:32 -05:00
Nguyen Anh Quynh d0125eb8bf regress: add invalid_write.py to test issue #371 2016-01-13 11:35:09 +08:00
Nguyen Anh Quynh 7de48f2f75 regress: add emu_clear_errors to .gitignore 2016-01-12 01:02:45 +08:00
Nguyen Anh Quynh e1fe63ae13 regress: fix compilation warnings for emu_clear_errors.c 2016-01-12 00:37:15 +08:00
Nguyen Anh Quynh fa430b4ad4 Merge branch 'test/issue-351' of https://github.com/williballenthin/unicorn into williballenthin-test/issue-351 2016-01-12 00:22:33 +08:00
Willi Ballenthin a9d4b4cfa7 add test case in C demonstrating issue 351 2016-01-11 09:57:13 -05:00
Nguyen Anh Quynh f4a5273ce7 Merge pull request #365 from williballenthin/test/issue-351 
add test case demonstrating issue 351
 2016-01-11 16:13:52 +08:00
Ryan Hileman b6db70808d add regress for #366 2016-01-10 23:51:11 -08:00
Willi Ballenthin b2b1d0be01 add test case demonstrating issue 351 2016-01-10 23:56:34 -05:00
farmdve 264c4c1b54 Add some fixes to the tests. 
My mem_nofree test fails on the latest code as apparently my address and
sizes overlap each other.

The mem_unmap test failed as the invalid memory hook case was incorrect.
 2016-01-05 18:02:54 +02:00
Nguyen Anh Quynh 06108ea908 regress: add rep_hook.py 2016-01-01 10:44:08 +08:00
Nguyen Anh Quynh 91501bc2d1 unit: modify the testcase #349 to reflect the recent change on the semantics of uc_mem_map() 2015-12-30 09:19:34 +08:00
Nguyen Anh Quynh 6e534417f1 unit: change clang -> CC 2015-12-30 08:50:58 +08:00
coco fa2da819b6 added test for unmap of doubly mapped region 2015-12-28 22:02:31 +01:00
Nguyen Anh Quynh 99b401c609 Merge branch 'la-fixed' of https://github.com/JCYang/unicorn into JCYang-la-fixed 2015-12-28 12:21:31 +08:00
Justin Campbell 9da93af861 Removed commented out code from MIPS kernel MMU test 2015-12-28 00:36:56 +00:00
Justin Campbell 822198ad16 Added new regression test for ability to execute MIPS at KSEG0 and higher when in kernel mode 2015-12-28 00:34:26 +00:00
Spl3en c9f6648877 Add sysenter_hook_x86 to tests/regress/Makefile and sysenter_hook_x86 to .gitignore. 2015-12-24 18:25:35 +01:00
Spl3en 4c3ad139ea (Fix #341) SYSENTER instruction is not properly hooked with uc_hook_add in x86 emulation. 
helper_sysenter in qemu/target-i386/seg_helper.c didn't check properly if a call interrupt callback was registred.
It has been fixed by copying the helper_syscall behavior.
 2015-12-24 16:00:22 +01:00
Nguyen Anh Quynh ed319bda0b x86: identity map guest address to host address. this fixes issue #300 2015-12-24 09:51:17 +08:00
Nguyen Anh Quynh 2984901f62 regress: fix testcase hook_code_add_del.py 2015-12-23 01:45:29 +08:00