7 commits

Author	SHA1	Message	Date
Craig Janeczek	8429d98b40	target/mips: Define a bit for MXU in insn_flags ... Define a bit for MXU in insn_flags. This is the first non-MIPS (third party) ASE supported in QEMU for MIPS, so it is placed in the section "bits 56-63: vendor-specific ASEs". Backports commit a031ac61619294ae473a78d1834e757fad8b59e5 from qemu	2018-11-11 05:52:18 -05:00
Fredrik Noring	93fb8273c8	target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants ... The R5900 implements the 64-bit MIPS III instruction set except DMULT, DMULTU, DDIV, DDIVU, LL, SC, LLD and SCD. The MIPS IV instructions MOVN, MOVZ and PREF are implemented. It has the R5900-specific three-operand instructions MADD, MADDU, MULT and MULTU as well as pipeline 1 versions MULT1, MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1. A set of 93 128-bit multimedia instructions specific to the R5900 is also implemented. The Toshiba TX System RISC TX79 Core Architecture manual: https://wiki.qemu.org/File:C790.pdf describes the C790 processor that is a follow-up to the R5900. There are a few notable differences in that the R5900 FPU - is not IEEE 754-1985 compliant, - does not implement double format, and - its machine code is nonstandard. Backports commit 6f692818a7b53630702d25a709cd61282fd139ad from qemu	2018-11-10 11:29:25 -05:00
Stefan Markovic	64bec62433	target/mips: Improve DSP R2/R3-related naming ... Do following replacements: ASE_DSPR2 -> ASE_DSP_R2 ASE_DSPR3 -> ASE_DSP_R3 MIPS_HFLAG_DSPR2 -> MIPS_HFLAG_DSP_R2 MIPS_HFLAG_DSPR3 -> MIPS_HFLAG_DSP_R3 check_dspr2() -> check_dsp_r2() check_dspr3() -> check_dsp_r3() and several other similar minor replacements. Backports commit 908f6be1b9cbc270470230f805d6f7474ab3178d from qemu	2018-10-23 13:42:01 -04:00
Stefan Markovic	071fe91d6a	target/mips: Add bit definitions for DSP R3 ASE ... Add DSP R3 ASE related bit definition for insn_flags and hflags. Backports commit 6208f09441dcf8d142ff0e1624ef12da298776a4 from qemu	2018-10-23 13:19:18 -04:00
Philippe Mathieu-Daudé	2a27a61c51	target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags) ... Distribute bits 56-63 vendor-specific ASEs as follows: - bits 0-31 MIPS base instruction sets - bits 32-47 MIPS ASEs - bits 48-55 vendor-specific base instruction sets - bits 56-63 vendor-specific ASEs Backports commit 45ebdd24c3de158890ce390df39855a891e80701 from qemu	2018-10-23 13:18:11 -04:00
Aleksandar Markovic	31f42b9f2c	target/mips: Add preprocessor constants for nanoMIPS ... Add ISA_NANOMIPS32 and CPU_NANOMIPS32 preprocessor constants. Backports commit fa7c0c9f5bc12970858a89f46dd5012c01545b80 from qemu	2018-08-27 04:11:21 -04:00
Thomas Huth	b2f1326437	Move target-* CPU file into a target/ folder ... We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Backports commit fcf5ef2ab52c621a4617ebbef36bf43b4003f4c0 from qemu	2018-03-01 22:50:58 -05:00

Renamed from qemu/target-mips/mips-defs.h (Browse further)