Commit graph

7191 commits

Author SHA1 Message Date
Richard Henderson fac4e416c9 target/arm: Update PFIRST, PNEXT for pred_desc
These two were odd, in that do_pfirst_pnext passed the
count of 64-bit words rather than bytes. Change to pass
the standard pred_full_reg_size to avoid confusion.

Backports 86300b5d044064046395ae8ed605cc19e63f2a7c
2021-03-04 15:09:47 -05:00
Richard Henderson 4ef4735cd3 target/arm: Introduce PREDDESC field definitions
SVE predicate operations cannot use the "usual" simd_desc
encoding, because the lengths are not a multiple of 8.
But we were abusing the SIMD_* fields to store values anyway.
This abuse broke when SIMD_OPRSZ_BITS was modified in e2e7168a214.

Introduce a new set of field definitions for exclusive use
of predicates, so that it is obvious what kind of predicate
we are manipulating. To be used in future patches

Backports b64ee454a4a086ed459bcda4c0bbb54e197841e4
2021-03-04 15:08:32 -05:00
Rémi Denis-Courmont 9dfa469976 target/arm: refactor vae1_tlbmask()
Backports bc944d3a8b305029196a5e1406702a92fa0b94cf
2021-03-04 15:05:54 -05:00
Rémi Denis-Courmont 8aeaff9385 target/arm: enable Secure EL2 in max CPU
Backports 24179fea7e34c4952d4878ae1b26108ba65e5933
2021-03-04 15:04:43 -05:00
Rémi Denis-Courmont e6d32dc2e0 target/arm: Implement SCR_EL2.EEL2
This adds handling for the SCR_EL3.EEL2 bit.

Backports 926c1b97895879b78ca14bca2831c08740ed1c38
2021-03-04 15:03:08 -05:00
Rémi Denis-Courmont 9690ed8236 target/arm: revector to run-time pick target EL
On ARMv8-A, accesses by 32-bit secure EL1 to monitor registers trap to
the upper (64-bit) EL. With Secure EL2 support, we can no longer assume
that that is always EL3, so make room for the value to be computed at
run-time.

Backports 6b340aeb48e4f7f983e1c38790de65ae93079840
2021-03-04 14:59:14 -05:00
Rémi Denis-Courmont ce8872709f target/arm: set HPFAR_EL2.NS on secure stage 2 faults
Backport 9861248f637ecf11113b04b0b5c7b13c9aa06f09
2021-03-04 14:54:33 -05:00
Rémi Denis-Courmont b49531cfef target/arm: secure stage 2 translation regime
b1a10c868f9b2b09e64009b43450e9a86697d9f3
2021-03-04 14:49:33 -05:00
Rémi Denis-Courmont eeefc3c4a2 target/arm: generalize 2-stage page-walk condition
The stage_1_mmu_idx() already effectively keeps track of which
translation regimes have two stages. Don't hard-code another test.

Backports 7879460a6149ed5e80c29cac85449191d9c5754a
2021-03-04 14:26:22 -05:00
Rémi Denis-Courmont 07ebb7f7ba target/arm: translate NS bit in page-walks
588c6dd113b27b8db393c7264297b9d33261692e
2021-03-04 14:25:13 -05:00
Rémi Denis-Courmont 6f57520b1d target/arm: do S1_ptw_translate() before address space lookup
In the secure stage 2 translation regime, the VSTCR.SW and VTCR.NSW
bits can invert the secure flag for pagetable walks. This patchset
allows S1_ptw_translate() to change the non-secure bit.

Backports 3d4bd397433b12b148d150c8bc5655a696389bd1
2021-03-04 14:23:43 -05:00
Rémi Denis-Courmont ce50ba6d07 target/arm: handle VMID change in secure state
The VTTBR write callback so far assumes that the underlying VM lies in
non-secure state. This handles the secure state scenario.

backports c4f060e89effd70ebdb23d3315495d33af377a09
2021-03-04 14:20:47 -05:00
Rémi Denis-Courmont a78c31e36a target/arm: add ARMv8.4-SEL2 system registers
Backports e9152ee91cc39ed8a53d03607e6e980a7e9444e6
2021-03-04 14:20:10 -05:00
Rémi Denis-Courmont edd5f021e6 target/arm: add MMU stage 1 for Secure EL2
This adds the MMU indices for EL2 stage 1 in secure state.

To keep code contained, which is largelly identical between secure and
non-secure modes, the MMU indices are reassigned. The new assignments
provide a systematic pattern with a non-secure bit.

Backports b6ad6062f1e55bd5b9407ce89e55e3a08b83827c
2021-03-04 14:16:31 -05:00
Rémi Denis-Courmont fbdcef3ca5 target/arm: add 64-bit S-EL2 to EL exception table
With the ARMv8.4-SEL2 extension, EL2 is a legal exception level in
secure mode, though it can only be AArch64.

This patch adds the target EL for exceptions from 64-bit S-EL2.

It also fixes the target EL to EL2 when HCR.{A,F,I}MO are set in secure
mode. Those values were never used in practice as the effective value of
HCR was always 0 in secure mode.

Backports 6c85f906261226e87211506bd9f787fd48a09f17
2021-03-04 14:00:23 -05:00
Rémi Denis-Courmont 159043008f target/arm: Define isar_feature function to test for presence of SEL2
Backports 5ca192dfc551c8a40871c4e30a8b8ceb879adc31
2021-03-04 13:58:57 -05:00
Rémi Denis-Courmont b42e6d6036 target/arm: factor MDCR_EL2 common handling
This adds a common helper to compute the effective value of MDCR_EL2.
That is the actual value if EL2 is enabled in the current security
context, or 0 elsewise.

Backports 59dd089cf9e4a9cddee596c8a1378620df51b9bb
2021-03-04 13:57:34 -05:00
Rémi Denis-Courmont b657bfc59b target/arm: use arm_hcr_el2_eff() where applicable
This will simplify accessing HCR conditionally in secure state.

Backports e04a5752cb03e066d7b1e583e340c7982fcd5e4e
2021-03-04 13:53:30 -05:00
Rémi Denis-Courmont 58af3e76e6 target/arm: use arm_is_el2_enabled() where applicable
Do not assume that EL2 is available in and only in non-secure context.
That equivalence is broken by ARMv8.4-SEL2.

Backports e6ef0169264b00cce552404f689ce137018ff290
2021-03-04 13:49:19 -05:00
Rémi Denis-Courmont 7a694223ca target/arm: add arm_is_el2_enabled() helper
This checks if EL2 is enabled (meaning EL2 registers take effects) in
the current security context.

Backports f3ee5160ce3c03795a28e16d1a0b4916a6c959f4
2021-03-04 13:44:04 -05:00
Rémi Denis-Courmont 7402645436 target/arm: remove redundant tests
In this context, the HCR value is the effective value, and thus is
zero in secure mode. The tests for HCR.{F,I}MO are sufficient.

Backports cc974d5cd84ea60a3dad59752aea712f3d47f8ce
2021-03-04 13:42:12 -05:00
Richard Henderson f6973abb3e target/arm: Add cpu properties to control pauth
The crypto overhead of emulating pauth can be significant for
some workloads. Add two boolean properties that allows the
feature to be turned off, on with the architected algorithm,
or on with an implementation defined algorithm.

We need two intermediate booleans to control the state while
parsing properties lest we clobber ID_AA64ISAR1 into an invalid
intermediate state.

Backports relevent members from eb94284d0812b4e7c11c5d075b584100ac1c1b9a
2021-03-04 13:40:27 -05:00
Richard Henderson 0332498752 target/arm: Implement an IMPDEF pauth algorithm
Without hardware acceleration, a cryptographically strong
algorithm is too expensive for pauth_computepac.

Even with hardware accel, we are not currently expecting
to link the linux-user binaries to any crypto libraries,
and doing so would generally make the --static build fail.

So choose XXH64 as a reasonably quick and decent hash.

Backports 283fc52ade85eb50141f3b8b85f82b07d016cb17
2021-03-04 13:38:22 -05:00
Philippe Mathieu-Daudé 296c32a8da decodetree: Open files with encoding='utf-8'
When decodetree.py was added in commit 568ae7efae7, QEMU was
using Python 2 which happily reads UTF-8 files in text mode.
Python 3 requires either UTF-8 locale or an explicit encoding
passed to open(). Now that Python 3 is required, explicit
UTF-8 encoding for decodetree source files.

To avoid further problems with the user locale, also explicit
UTF-8 encoding for the generated C files.

Explicit both input/output are plain text by using the 't' mode.

This fixes:

$ /usr/bin/python3 scripts/decodetree.py test.decode
Traceback (most recent call last):
File "scripts/decodetree.py", line 1397, in <module>
main()
File "scripts/decodetree.py", line 1308, in main
parse_file(f, toppat)
File "scripts/decodetree.py", line 994, in parse_file
for line in f:
File "/usr/lib/python3.6/encodings/ascii.py", line 26, in decode
return codecs.ascii_decode(input, self.errors)[0]
UnicodeDecodeError: 'ascii' codec can't decode byte 0xc3 in position 80:
ordinal not in range(128)

Backports 4cacecaaa2bbf8af0967bd3eee43297fada475a9
2021-03-04 13:34:08 -05:00
Richard Henderson 419941c3d1 tcg: Remove tcg_gen_dup{8,16,32,64}i_vec
These interfaces have been replaced by tcg_gen_dupi_vec
and tcg_constant_vec.

Backports be986adb35e3594b02ee0d7f1cbec96b08bb29b7
2021-03-04 13:32:32 -05:00
Richard Henderson 8975559888 tcg/i386: Use tcg_constant_vec with tcg vec expanders
Backports 9739a052ad313dbc9b1224f91f23f38e692d3f7e
2021-03-04 13:28:55 -05:00
Richard Henderson 1b811b8546 tcg: Add tcg_reg_alloc_dup2
There are several ways we can expand a vector dup of a 64-bit
element on a 32-bit host.

Backports efe86b21ead9b5d256ce90c378e31681c5e243a5
2021-03-04 13:20:00 -05:00
Richard Henderson 471fc98c49 tcg: Remove movi and dupi opcodes
These are now completely covered by mov from a
TYPE_CONST temporary.

Backports c58f4c97b2ad9247c5ee85d625a934370862fba1
2021-03-04 13:14:30 -05:00
Richard Henderson 6e38e5004f tcg: Use tcg_constant_{i32,i64,vec} with gvec expanders
Backports 88d4005b098427638d7551aa04ebde4fdd06835b
2021-03-04 13:05:25 -05:00
Richard Henderson bd7e78fe4b tcg: Use tcg_constant_{i32,i64} with tcg int expanders
Backports 11d11d61bd9e82ac917c8159f6a2b736829231ae
2021-03-04 12:46:13 -05:00
Richard Henderson 6e54b46d28 tcg: Convert tcg_gen_dupi_vec to TCG_CONST
Because we now store uint64_t in TCGTemp, we can now always
store the full 64-bit duplicate immediate. So remove the
difference between 32- and 64-bit hosts.

Backports 0b4286dd15e2bcaf2aa53dfac0fb3103690f5a34
2021-03-04 12:19:48 -05:00
Richard Henderson 541ef541ae tcg/optimize: Use tcg_constant_internal with constant folding
Backport 8fe35e0444be88de4e3ab80a2a0e210a1f6d663d
2021-03-04 12:15:58 -05:00
Richard Henderson 0038cda620 tcg/optimize: Adjust TempOptInfo allocation
Do not allocate a large block for indexing. Instead, allocate
for each temporary as they are seen.

In general, this will use less memory, if we consider that most
TBs do not touch every target register. This also allows us to
allocate TempOptInfo for new temps created during optimization.

Backports 8f17a975e60b773d7c366a81c0d9bbe304f30859
2021-03-03 21:44:53 -05:00
Richard Henderson e751b45aea tcg/optimize: Improve find_better_copy
Prefer TEMP_CONST over anything else.

Backports 4c868ce6454872d395b29de8d82387b2ad14aeeb
2021-03-03 21:35:28 -05:00
Richard Henderson 8edc9b76dd tcg: Introduce TYPE_CONST temporaries
These will hold a single constant for the duration of the TB.
They are hashed, so that each value has one temp across the TB.

Not used yet, this is all infrastructure.

Backports c0522136adf550c7a0ef7c0755c1f9d1560d2757
2021-03-03 21:29:40 -05:00
Richard Henderson 6100deaffd tcg: Expand TempOptInfo to 64-bits
This propagates the extended value of TCGTemp.val that we did before.
In addition, it will be required for vector constants.

Backports 54795544e4cfb2fa198f7ca244b5ea9eaad322d4
2021-03-03 21:04:23 -05:00
Richard Henderson e84b88344a tcg: Rename struct tcg_temp_info to TempOptInfo
Fix this name vs our coding style.

Backports 6fcb98eda16b27d1999737346cdd4d3c1eae6a57
2021-03-03 20:52:59 -05:00
Richard Henderson 0f71f52216 tcg: Expand TCGTemp.val to 64-bits
This will reduce the differences between 32-bit and 64-bit hosts,
allowing full 64-bit constants to be created with the same interface.

Backports bdb38b95f72ebbef2d24e057828dd18ba9c81f63
2021-03-03 20:46:32 -05:00
Richard Henderson b49c4639d1 tcg: Add temp_readonly
In most, but not all, places that we check for TEMP_FIXED,
we are really testing that we do not modify the temporary.

Backports e01fa97dea857a35be5bb8cce0d632a62e72c689
2021-03-03 20:45:25 -05:00
Richard Henderson 30739864d2 tcg: Consolidate 3 bits into enum TCGTempKind
The temp_fixed, temp_global, temp_local bits are all related.
Combine them into a single enumeration.

Backports ee17db83d2dce35792e9bf03366af193e5e0e5c9
2021-03-03 20:41:24 -05:00
Richard Henderson 520ec7ca76 tcg: Increase tcg_out_dupi_vec immediate to int64_t
While we don't store more than tcg_target_long in TCGTemp,
we shouldn't be limited to that for code generation. We will
be able to use this for INDEX_op_dup2_vec with 2 constants.

Also pass along the minimal vece that may be said to apply
to the constant. This allows some simplification in the
various backends.

Backports 4e18617555955503628a004ed97e1fc2fa7818b9
2021-03-03 20:27:39 -05:00
Richard Henderson c5c19529c5 tcg: Use tcg_out_dupi_vec from temp_load
Having dupi pass though movi is confusing and arguably wrong.

Backports 0a6a8bc8ebfe5ae2a3f18ef48b92a74bc2df2f96
2021-03-03 20:23:02 -05:00
Peter Maydell 68f645dd4f target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
In commit cd8be50e58f63413c0 we converted the A32 coprocessor
insns to decodetree. This accidentally broke XScale/iWMMXt insns,
because it moved the handling of "cp insns which are handled
by looking up the cp register in the hashtable" from after the
call to the legacy disas_xscale_insn() decode to before it,
with the result that all XScale/iWMMXt insns now UNDEF.

Update valid_cp() so that it knows that on XScale cp 0 and 1
are not standard coprocessor instructions; this will cause
the decodetree trans_ functions to ignore them, so that
execution will correctly get through to the legacy decode again.

Backports e4d51ac6921dc861bfb3d20e4c7dcf345840a9da
2021-03-03 20:17:20 -05:00
Leif Lindholm 09fd12e5f2 target/arm: add aarch32 ID register fields to cpu.h
Add entries present in ARM DDI 0487F.c (August 2020).

Backports bd78b6be24f3ceb71f1a7ec2c98c7a5e49cb4a86
2021-03-03 20:16:26 -05:00
Leif Lindholm a2faae9e30 target/arm: add aarch64 ID register fields to cpu.h
Add entries present in ARM DDI 0487F.c (August 2020).

Backports 00a92832f453275ca023962c00a60dde3a4f2fed
2021-03-03 20:15:16 -05:00
Leif Lindholm ba891afd32 target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
Backports 2a14526a6f56973348d622abc572db377f5a23ef
2021-03-03 20:14:05 -05:00
Leif Lindholm fc8e5fe38d target/arm: make ARMCPU.ctr 64-bit
When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the
TminLine field in bits [37:32].
Extend the ctr field to be able to hold this context.

Backports a5fd319ae7f6d496ff5448ec1dedcae8e2f59e9f
2021-03-03 20:13:20 -05:00
Leif Lindholm e6eb25f75a target/arm: make ARMCPU.clidr 64-bit
The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
32, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
Extend the clidr field to be able to hold this context.

Backports f6450bcb6b2d3e4beae77141edce9e99cb8c277e
2021-03-03 20:12:48 -05:00
Leif Lindholm 3fff83e48f target/arm: fix typo in cpu.h ID_AA64PFR1 field name
SBSS -> SSBS

Backports 9a286bcdfd2b04afca9a668a6d6e0feb809d2d63
2021-03-03 20:12:08 -05:00
Rémi Denis-Courmont 6f06f383ea target/arm: enable Small Translation tables in max CPU
Backports 078e9fe3cbd6894fb6e420d8b53f304a3d5c0464
2021-03-03 20:11:10 -05:00