unicorn/qemu
Alistair Francis 1001f0ba1f target/riscv: Correctly implement TSR trap
As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't
correctly handling illegal instructions based on the value of MSTATUS_TSR
and the current privledge level.

This patch fixes the issue raised in the bug by raising an illegal
instruction if TSR is set and we are in S-Mode.

Backports commit ed5abf46b3c414ef58e647145f19b3966700b206 from qemu
2020-04-30 06:19:49 -04:00
..
accel Ensure that PC is not fixed up when code tracing or timing. (#1179) 2020-01-14 09:52:25 -05:00
crypto
default-configs target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
docs docs/devel/memory.txt: Document _with_attrs accessors 2018-10-04 04:46:26 -04:00
fpu fpu: rename softfloat-specialize.h -> .inc.c 2019-11-18 21:12:30 -05:00
hw Expose different 32-bit ARM CPU models to users via UC_MODE flags (#1165) 2020-01-14 09:37:21 -05:00
include tcg: Add support for a helper with 7 arguments 2020-03-21 16:53:56 -04:00
qapi qapi: Rewrite string-input-visitor's integer and list parsing 2018-12-18 04:57:25 -05:00
qobject qstring: Move qstring_from_substr()'s @end one to the right 2018-08-02 21:24:19 -04:00
qom cpu: Move icount_decr to CPUNegativeOffsetState 2019-06-13 15:34:28 -04:00
scripts decodetree: Suppress redundant declaration warnings 2019-11-18 21:21:30 -05:00
target target/riscv: Correctly implement TSR trap 2020-04-30 06:19:49 -04:00
tcg tcg: Add tcg_gen_gvec_5_ptr 2020-03-21 16:54:01 -04:00
util util/cutils: Turn FIXME comment into QEMU_BUILD_BUG_ON() 2020-01-14 08:04:30 -05:00
aarch64.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
aarch64eb.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
accel.c
arm.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
armeb.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
CODING_STYLE.rst docs: split the CODING_STYLE doc into distinct groups 2019-11-28 02:54:44 -05:00
configure configure: Require Python >= 3.5 2020-01-14 08:09:23 -05:00
COPYING
COPYING.LIB
cpus.c Include qapi/error.h exactly where needed 2018-03-07 12:26:38 -05:00
exec.c Memory: Enable writeback for given memory region 2020-01-14 07:44:24 -05:00
gen_all_header.sh
glib_compat.c target/arm: Add VHE system register redirection and aliasing 2020-03-21 15:57:03 -04:00
header_gen.py header_gen: Add gen_{u,s}shl_i{32,64} to arm 2020-04-13 19:38:59 +01:00
ioport.c
LICENSE
m68k.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
Makefile Makefile: Rename targets for make recursion 2019-08-08 17:26:49 -04:00
Makefile.objs qapi: Move qapi-schema.json to qapi/, rename generated files 2018-03-09 11:35:11 -05:00
Makefile.target configure: Remove old -fno-gcse workaround for GCC 4.6.x and 4.7.[012] 2018-12-18 03:52:36 -05:00
memory.c Memory: Enable writeback for given memory region 2020-01-14 07:44:24 -05:00
memory_ldst.inc.c memory: Single byte swap along the I/O path 2020-01-07 19:12:04 -05:00
memory_mapping.c
mips.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
mips64.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
mips64el.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
mipsel.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
powerpc.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
qemu-timer.c
riscv32.h target/riscv: Emulate TIME CSRs for privileged mode 2020-03-22 02:22:17 -04:00
riscv64.h target/riscv: Emulate TIME CSRs for privileged mode 2020-03-22 02:22:17 -04:00
rules.mak build-sys: silence make by default or V=0 2018-03-06 08:58:03 -05:00
sparc.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
sparc64.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00
unicorn_common.h unicorn_common: Fix unicorn memory functions failing 2018-09-03 10:40:14 -04:00
VERSION Open 5.0 development tree 2020-01-07 17:50:51 -05:00
vl.c Use cpu_create(type) instead of cpu_init(cpu_model) 2018-03-20 14:20:30 -04:00
vl.h
x86_64.h target/arm: Convert PMULL.8 to gvec 2020-03-21 19:35:46 -04:00