unicorn/qemu/target
Craig Janeczek 58dc377890
target/mips: Introduce MXU registers
Define and initialize the 16 MXU registers - 15 general computational
register, and 1 control register). There is also a zero register, but
it does not have any corresponding variable.

Backports commit eb5559f67dc8dc12335dd996877bb6daaea32eb2 from qemu.
2018-11-11 05:50:52 -05:00
..
arm target/arm: Only flush tlb if ASID changes 2018-11-10 11:26:24 -05:00
i386 target/i386: Convert to HAVE_CMPXCHG128 2018-10-23 15:21:03 -04:00
m68k Removes accessible assert 2018-10-06 05:02:20 -04:00
mips target/mips: Introduce MXU registers 2018-11-11 05:50:52 -05:00
sparc Sparc increase ttl number 2018-10-06 04:55:52 -04:00