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0c3e33ee11
If EL3 is AArch32, then the secure physical timer is accessed via banking of the registers used for the non-secure physical timer. Implement this banking. Note that the access controls for the AArch32 banked registers remain the same as the physical-timer checks; they are not the same as the controls on the AArch64 secure timer registers. Backports commit 9ff9dd3c875956523bb4c19ca712e5d05aab3c65 from qemu |
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| .. | ||
| arm_ldst.h | ||
| cpu-qom.h | ||
| cpu.c | ||
| cpu.h | ||
| cpu64.c | ||
| crypto_helper.c | ||
| helper-a64.c | ||
| helper-a64.h | ||
| helper.c | ||
| helper.h | ||
| internals.h | ||
| iwmmxt_helper.c | ||
| kvm-consts.h | ||
| Makefile.objs | ||
| neon_helper.c | ||
| op_addsub.h | ||
| op_helper.c | ||
| psci.c | ||
| translate-a64.c | ||
| translate.c | ||
| translate.h | ||
| unicorn.h | ||
| unicorn_aarch64.c | ||
| unicorn_arm.c | ||