Jiaxun Yang 5ca33a4aaa target/mips: Fix loongson multimedia condition instructions ... Loongson multimedia condition instructions were previously implemented as write 0 to rd due to lack of documentation. So I just confirmed with Loongson about their encoding and implemented them correctly. Backports commit 84878f4c00a7beca1d1460e2f77a6c833b8d0393 from qemu		2020-04-30 07:14:10 -04:00
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cp0_timer.c	target/mips: Style improvements in cp0_timer.c	2019-11-18 21:24:37 -05:00
cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 19:35:46 -04:00
cpu-qom.h	mips: MIPSCPU model subclasses	2018-03-05 00:42:29 -05:00
cpu.c	target/mips: Switch to do_transaction_failed() hook	2019-11-28 02:54:53 -05:00
cpu.h	target/mips: Add implementation of GINVT instruction	2020-03-21 13:01:35 -04:00
dsp_helper.c	target/mips: Clean up dsp_helper.c	2019-06-03 11:14:31 -04:00
helper.c	target/mips: Add implementation of GINVT instruction	2020-03-21 13:01:35 -04:00
helper.h	target/mips: Add implementation of GINVT instruction	2020-03-21 13:01:35 -04:00
internal.h	target/mips: Add implementation of GINVT instruction	2020-03-21 13:01:35 -04:00
lmi_helper.c	target/mips: Clean up lmi_helper.c	2019-06-03 11:15:34 -04:00
Makefile.objs	mips: introduce internal.h and cleanup cpu.h	2018-03-05 00:25:56 -05:00
mips-defs.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 19:35:46 -04:00
msa_helper.c	target/mips: rationalise softfloat includes	2019-11-18 21:15:19 -05:00
op_helper.c	target/arm: fix TCG leak for fcvt half->double	2020-03-21 13:14:47 -04:00
TODO	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
translate.c	target/mips: Fix loongson multimedia condition instructions	2020-04-30 07:14:10 -04:00
translate_init.c	target/mips: Use env_cpu, env_archcpu	2019-06-12 11:55:43 -04:00
unicorn.c	Removed hardcoded CP0C3_ULRI (#1098)	2019-08-08 20:08:57 -04:00
unicorn.h	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00