unicorn/qemu/target/riscv
Jim Shu 85ccd1a71e target/riscv: flush TLB pages if PMP permission has been changed
If PMP permission of any address has been changed by updating PMP entry,
flush all TLB pages to prevent from getting old permission.

Backports 2c2e0f2842520bcd25472285cfce39696e52e662
2021-03-30 15:09:12 -04:00
..
insn_trans target/riscv: Split the Hypervisor execute load helpers 2021-03-08 15:14:47 -05:00
cpu-param.h target/riscv: Add a virtualised MMU Mode 2021-03-08 14:56:14 -05:00
cpu.c target/riscv: Add a riscv_cpu_is_32bit() helper function 2021-03-08 15:26:57 -05:00
cpu.h target/riscv: Add a riscv_cpu_is_32bit() helper function 2021-03-08 15:26:57 -05:00
cpu_bits.h target/riscv: csr: Remove compile time XLEN checks 2021-03-08 15:34:30 -05:00
cpu_helper.c target/riscv: add log of PMP permission checking 2021-03-30 15:07:52 -04:00
cpu_user.h Supply missing header guards 2019-06-12 10:59:10 -04:00
csr.c target/riscv: fix vs() to return proper error code 2021-03-30 14:59:37 -04:00
fpu_helper.c target/riscv: fpu_helper: Match function defs in HELPER macros 2021-03-08 15:25:30 -05:00
helper.h target/riscv: fpu_helper: Match function defs in HELPER macros 2021-03-08 15:25:30 -05:00
insn16-32.decode target/riscv: Split RVC32 and RVC64 insns into separate files 2019-05-28 19:00:23 -04:00
insn16-64.decode target/riscv: Add checks for several RVC reserved operands 2019-05-28 19:20:36 -04:00
insn16.decode target/riscv: Add checks for several RVC reserved operands 2019-05-28 19:20:36 -04:00
insn32-64.decode target/riscv: Allow generating hlv/hlvx/hsv instructions 2021-03-08 13:13:32 -05:00
insn32.decode target/riscv: Allow generating hlv/hlvx/hsv instructions 2021-03-08 13:13:32 -05:00
instmap.h Supply missing header guards 2019-06-12 10:59:10 -04:00
internals.h target/riscv: Check nanboxed inputs to fp helpers 2021-03-08 12:31:18 -05:00
Makefile.objs target/riscv: add vector configure instruction 2021-02-26 02:37:59 -05:00
op_helper.c target/riscv/pmp: Raise exception if no PMP entry is configured 2021-03-08 15:39:55 -05:00
pmp.c target/riscv: flush TLB pages if PMP permission has been changed 2021-03-30 15:09:12 -04:00
pmp.h target/riscv: propagate PMP permission to TLB page 2021-03-30 15:05:40 -04:00
translate.c target/riscv: Remove the hyp load and store functions 2021-03-08 15:11:11 -05:00
unicorn.c target/riscv: Add the virtulisation mode 2020-03-22 01:15:06 -04:00
unicorn.h target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
vector_helper.c target/riscv/vector_helper: Fix build on 32-bit big endian hosts 2021-03-08 12:18:39 -05:00