unicorn/qemu/target-i386
Eduardo Habkost c3a0cba5b1
target-i386: Don't try to enable PT State xsave component
The code that calculates the set of supported XSAVE components on
CPUID looks at ext_save_areas to find out which components should
be enabled. However, if there are zeroed entries in the
ext_save_areas array, the
((env->features[esa->feature] & esa->bits) == esa->bits)
check will always succeed and QEMU will unconditionally try to
enable the component.

Luckily this never caused any problems because the only missing
entry in ext_save_areas is the PT State component (bit 8), and
KVM currently doesn't support it (so it was cleared on ena_mask).
But the code was still incorrect and would break if KVM starts
returning CPUID[EAX=0xD,ECX=0].EAX[bit 8] as supported on
GET_SUPPORTED_CPUID.

Fix the problem by changing the code to not enable a XSAVE
component if ExtSaveArea::bits is zero.

Backports commit 9646f4927faf68e8690588c2fd6dc9834c440b58 from qemu
2018-02-26 04:30:35 -05:00
..
arch_memory_mapping.c x86: Clean up includes 2018-02-19 01:00:09 -05:00
bpt_helper.c cpu-exec: Rename cpu_resume_from_signal() to cpu_loop_exit_noexc() 2018-02-24 17:25:28 -05:00
cc_helper.c target-i386: Perform set/reset_inhibit_irq inline 2018-02-20 13:34:47 -05:00
cc_helper_template.h This code should now build the x86_x64-softmmu part 2. 2017-01-19 22:50:28 +11:00
cpu-qom.h target-i386: make cpu-qom.h not target specific 2018-02-24 00:55:22 -05:00
cpu.c target-i386: Don't try to enable PT State xsave component 2018-02-26 04:30:35 -05:00
cpu.h target-i386: Automatically set level/xlevel/xlevel2 when needed 2018-02-26 04:03:09 -05:00
excp_helper.c cpu: move exec-all.h inclusion out of cpu.h 2018-02-24 02:39:08 -05:00
fpu_helper.c target-i386: Use struct X86XSaveArea in fpu_helper.c 2018-02-26 03:38:53 -05:00
helper.c target-i386: Move user-mode exception actions out of user-exec.c 2018-02-24 17:27:08 -05:00
helper.h target-i386: implement PKE for TCG 2018-02-22 10:18:55 -05:00
int_helper.c cpu: move exec-all.h inclusion out of cpu.h 2018-02-24 02:39:08 -05:00
Makefile.objs target-i386: Enable control registers for MPX 2018-02-20 13:27:46 -05:00
mem_helper.c Fix confusing argument names in some common functions 2018-02-25 03:58:27 -05:00
misc_helper.c cpu: move exec-all.h inclusion out of cpu.h 2018-02-24 02:39:08 -05:00
mpx_helper.c cpu: move exec-all.h inclusion out of cpu.h 2018-02-24 02:39:08 -05:00
ops_sse.h target-i386: Rename XMM_[BWLSDQ] helpers to ZMM_* 2018-02-18 23:53:16 -05:00
ops_sse_header.h target-i386: Rename struct XMMReg to ZMMReg 2018-02-18 23:46:30 -05:00
seg_helper.c target-i386: Fixed syscall posssible segfault 2018-02-26 02:36:09 -05:00
shift_helper_template.h This code should now build the x86_x64-softmmu part 2. 2017-01-19 22:50:28 +11:00
smm_helper.c target-i386: Include log.h in smm_helper 2018-02-24 03:06:07 -05:00
svm.h Clean up ill-advised or unusual header guards 2018-02-25 04:22:46 -05:00
svm_helper.c cpu: move exec-all.h inclusion out of cpu.h 2018-02-24 02:39:08 -05:00
TODO import 2015-08-21 15:04:50 +08:00
topology.h pc: Add x86_topo_ids_from_apicid() 2018-02-25 20:31:36 -05:00
translate.c target-i386: Generate fences for x86 2018-02-26 03:28:31 -05:00
unicorn.c qemu-common: push cpu.h inclusion out of qemu-common.h 2018-02-24 01:50:56 -05:00
unicorn.h New feature: registers can be bulk saved/restored in an opaque blob 2016-08-20 04:14:07 -07:00