Bin Meng d508a74a74 target/riscv: cpu: Add a new 'resetvec' property ... Currently the reset vector address is hard-coded in a RISC-V CPU's instance_init() routine. In a real world we can have 2 exact same CPUs except for the reset vector address, which is pretty common in the RISC-V core IP licensing business. Normally reset vector address is a configurable parameter. Let's create a 64-bit property to store the reset vector address which covers both 32-bit and 64-bit CPUs. Backports 9b4c9b2b2a50fe4eb90d0ac2d8723b46ecb42511		2021-03-08 13:57:57 -05:00
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arm	target/arm/cpu: Update coding style to make checkpatch.pl happy	2021-03-08 11:35:28 -05:00
i386	i386: Fix build	2021-03-05 08:35:14 -05:00
m68k	m68k: Fix build	2021-03-05 08:29:53 -05:00
mips	mips: Fix build	2021-03-05 08:51:51 -05:00
riscv	target/riscv: cpu: Add a new 'resetvec' property	2021-03-08 13:57:57 -05:00
sparc	sparc: Fix build	2021-03-05 08:54:43 -05:00